( ESNUG 295 Item 6 ) ----------------------------------------------- [7/8/98]
From: "Chris Cope" <chrisc@ppsol.com>
Subject: 'Translate' Headaches With Buffering, dont_touch, & Incrementals
John,
We are attempting to translate a very large design from one technology to
another similar one.
Our first attempt was to load the big .db file in and let her rip. But the
major sub-blocks have dont-touches, so it didn't penetrate the hierarchy.
Our Synopsys rep told us that we would have to manually traverse the
hierarchy removing these for it to work. He said that using a:
remove_attribute find(design,"*",-hierarchy) dont_touch
would not even work (no real explanation given).
Rather than do that, we loaded the Verilog netlist of the entire design in
and ran translate on it. This worked great since all constraints and
attributes are not present. But, many of our buffer networks had been
removed. Apparently, Synopsys does some optimizing in the translate step.
Since we had no constraints, it decided that these buffers were not needed.
So we loaded each sub-block .db file and ran translate on that. This does
have constraint info. But, alas, our buffer network was still destroyed.
I am now trying an incremental compile. But this is so time-consuming, I'm
about to start over from VHDL.
I totally understand that translate must use some smarts when figuring out
how to map cells that don't exist in the new library. But a huge selection
of buffers do exist and it sees fit to just take them out. Any ideas on why
it does this? Or how to solve my original translation problem?
- Chris Cope
Pinpoint Solutions
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