( ESNUG 295 Item 7 ) ----------------------------------------------- [7/8/98]
Subject: (ESNUG 293 #9 292 #8) Synopsys VHDL Compiler Handling Of X"FF"
> Perhaps Anon is refering to the 1987 LRM in his message. Anon is however
> correct that the use of such a feature is not likely to be portable --
> especially in a world where the big guns can trample on standards simply
> because they feel like it.At any rate perhaps Cadence & Synopsys engineers
> should read the LRM and implement the language semantics as described.
>
> - Tim Davis
From: Murdo McKissock <mjm@sqf.hp.com>
1. Has anyone done a survey of which tools support the 1993 VHDL standard?
The Exemplar synthesis tools and Model Tech simulator claim full support
for VHDL'93 while Synopsys always used to be strictly VHDL'87. I wonder
about more recent Synopsys tools like FPGA Express?
Hex constants are handy, but direct instantiation of an entity without a
component would save much duplication in routine VHDL design entry.
2. Below is my package to implement hexadecimal literals. "hex" is shorter
than "To_StdLogicVector", is synthesizable, allows assignment to vectors
where the length is not a multiple of 4 and supports non-binary states.
Examples of use:
signal byte_val : std_logic_vector(7 downto 0);
signal odd_val : std_logic_vector(9 downto 0);
...
byte_val <= hex("5A");
odd_val <= hex("2FE",10);
byte_val <= hex("ZZ");
Package:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_arith.all;
package hex_util is
type hex_char is ('U', 'X', '0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'Z', '-');
type hex_vector is ARRAY(natural range <>) of hex_char;
function hex(b : hex_vector; width : integer := 0)
return std_logic_vector;
end hex_util;
package body hex_util is
function hex(b : hex_vector; width : integer := 0)
return std_logic_vector is
constant b_width : integer := b'length * 4;
variable result : std_logic_vector(b_width - 1 downto 0);
variable j : natural;
begin
j:= b_width;
for i in b'range loop -- Scan b from left to right
j:= j - 4;
case b(i) is
-- If the next line gives trouble in synthesis, you may be trying
-- to use "hex" with a non-static string argument. Changing this
-- line to assign "XXXX" would make it synthesizable, but the
-- compiler would have to work overtime to reduce the resulting
-- logic to a static value. Just look at an unmapped design!
when 'U' => result(j+3 downto j) := "UUUU";
when 'X' => result(j+3 downto j) := "XXXX";
when '0' => result(j+3 downto j) := "0000";
when '1' => result(j+3 downto j) := "0001";
when '2' => result(j+3 downto j) := "0010";
when '3' => result(j+3 downto j) := "0011";
when '4' => result(j+3 downto j) := "0100";
when '5' => result(j+3 downto j) := "0101";
when '6' => result(j+3 downto j) := "0110";
when '7' => result(j+3 downto j) := "0111";
when '8' => result(j+3 downto j) := "1000";
when '9' => result(j+3 downto j) := "1001";
when 'A' => result(j+3 downto j) := "1010";
when 'B' => result(j+3 downto j) := "1011";
when 'C' => result(j+3 downto j) := "1100";
when 'D' => result(j+3 downto j) := "1101";
when 'E' => result(j+3 downto j) := "1110";
when 'F' => result(j+3 downto j) := "1111";
when 'Z' => result(j+3 downto j) := "ZZZZ";
when '-' => result(j+3 downto j) := "----";
end case;
end loop;
if width > 0 then
for i in b_width - 1 downto width loop
assert result(i) /= '1' report
"Error: function hex tried to assign '1' to a non-existent bit";
end loop;
return result(width - 1 downto 0);
else
return result;
end if;
end;
end hex_util;
Hope this helps.
- Murdo McKissock
Hewlett-Packard Ltd.
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