( ESNUG 299 Item 4 ) ---------------------------------------------- [9/21/98]
Subject: Going From Synopsys Synthesis To Cadence Layout
> How can I get the synthesized code from Synopsys to Cadence to generate
> the layout ? I've read about the EDIF format, but it is incompatible.
>
> - Marek Ponca
> Technische Universitaet Ilmenau
From: Peter Sandberg <peters@cadence.com>
Hi Marek,
There are several alternatives available:
1. Have Design Compiler to generate Verilog and import the Verilog
directly into Silicon Ensemble to do P&R.
2. Have DC to generate Verilog and import into Physical Design Planner
and do floorplanning, timing analysis, congestion analysis, WLM model
generation, etc and then run SE from PDP. This will also give you the
option to use IC Craftsman for chip assembly from PDP.
3. Have DC to generate Verilog and import the netlist into DFII using
VerilogIn and then through Preview do floorplanning and run SE for P&R.
- Peter Sandberg
Cadence
---- ---- ---- ---- ---- ---- ----
From: "Matthias Brucke" <Matthias.Brucke@Informatik.Uni-Oldenburg.DE>
We used to use EDIF and use Verilog now (which works). Perhaps you have
a look at: "http://tech-www.informatik.uni-hamburg.de/Dokumentation
/DokuHomePage.html#Cadence" which is OK for you as these documents are
in German.
- Matthias Brucke
Universitaet Oldenburg
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