( ESNUG 299 Item 5 ) ---------------------------------------------- [9/21/98]
From: [ Stuck Up Ganges Creek Without A Paddle ]
Subject: Design Compiler (98.08 - 3.4b) Double "AND" Gates W/ Resets Problem
Hello John,
Please keep me anonymous.
We are seeing that Design Compiler is adding double "AND" gates when it is
not necessary. The created gate level netlist will has two AND2 gates at
the end of the path and both AND2's will have reset as one of the inputs.
+----+ sel_d1
|FLOP|-----------------+
+----+ |
|
+----+ vishnu_d1[0] |\|
|FLOP|---------------| \
+----+ |M | +----+
|U |------| | +----+
+----+ vishnu_d2[0] |X | |AND2|-----| | +----+
|FLOP|---------------| / +--| | |AND2|-----|FLOP|
+----+ |/ | +----+ +-| | +----+
| | +----+
+----+ soft_reset_10 | |
|FLOP|----------------------+-----------+
+----+
Here's our source code that creates this logic:
module krishna ( shiva_ptr, sel, vishnu, reset, clk );
output [5:0] shiva_ptr;
input sel;
input [5:0] vishnu;
input reset;
input clk;
reg soft_reset_10;
always @(posedge clk) soft_reset_10 <= reset;
// synopsys sync_set_reset "soft_reset_10"
reg [5:0] vishnu_d1, vishnu_d2;
reg [5:0] shiva_ptr;
reg sel_d1;
always @(posedge clk) begin
if (soft_reset_10) begin
sel_d1 <= 0;
end else begin
sel_d1 <= sel;
end
vishnu_d1[5:0] <= vishnu[5:0];
vishnu_d2[5:0] <= vishnu[5:0];
end
always @(posedge clk) begin
if (soft_reset_10)
shiva_ptr[5:0] <= 0;
else if (sel_d1)
shiva_ptr[5:0] <= vishnu_d1[5:0];
else
shiva_ptr[5:0] <= vishnu_d2[5:0];
end
endmodule
The apparent cause is using sync_set_reset and having a synchronous reset
flop with enable and having the enable* come from a flip-flop which is
itself reset by the same reset signal. (*- experimentation has shown that
having a reset on any of vishnu_d1, vishnu_d2 OR sel_d1 will cause this
same problem.)
The above example has been changed in RTL structure several times
(implemented as a CASE statement, if-else-if-else, as well as using a "?"
operator.) All results were identical.
While the circuit above is functionally correct, it is of course a
sub-optimal result. The same result was obtained using DC 98.08, 98.2,
and 3.4b.
- [ Stuck Up Ganges Creek Without A Paddle ]
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