( ESNUG 300 Item 6 ) ---------------------------------------------- [10/7/98]
Subject: ( ESNUG 299 #5 ) DC 98.08 - 3.4b Double "ANDs" W/ Resets Problem
> We are seeing that Design Compiler is adding double "AND" gates when it is
> not necessary. The created gate level netlist will has two AND2 gates at
> the end of the path and both AND2's will have reset as one of the inputs.
>
>
> +----+ sel_d1
> |FLOP|-----------------+
> +----+ |
> |
> +----+ vishnu_d1[0] |\|
> |FLOP|---------------| \
> +----+ |M | +----+
> |U |------| | +----+
> +----+ vishnu_d2[0] |X | |AND2|-----| | +----+
> |FLOP|---------------| / +--| | |AND2|-----|FLOP|
> +----+ |/ | +----+ +-| | +----+
> | | +----+
> +----+ soft_reset_10 | |
> |FLOP|----------------------+-----------+
> +----+
From: William Liao <wliao@vadem.com>
Hi, John,
I compiled the given code from this bug, and I did not have any problems.
In my case Design Compiler replaced the 2-1 mux and the two AND2 gates
with a complex gate 2-2 OR-NAND (two 2-input OR followed by one 2-input
NAND). I had no double gated ANDs that this user complained about.
- William Liao
Vadem
---- ---- ---- ---- ---- ---- ----
From: [ Stuck Up Ganges Creek Without A Paddle ]
Hello John:
Please keep me anonymous.
I'm the engineer who submitted the original problem.
While debugging the above problem, we manually deleted the second AND
gate and did a report_constraint -all_violators. The thinking behind doing
so was to check if Design Compiler was adding the second AND gate to fix
some design rule. No violations were reported by report_constraint.
We then added the following two lines to our synthesis script just
before the compile command.
set_cost_priority -delay
set_max_area <Integer>
where <Integer> is a number smaller than the area number reported in our
previous synthesis run. This solved the problem!
We still don't understand, though, why Design Compiler adds an additional
AND gate and then removes it during Area Optimization.
Thanks for your help.
- [ Stuck Up Ganges Creek Without A Paddle ]
|
|
