( ESNUG 300 Item 7 ) ---------------------------------------------- [10/7/98]
Subject: ( ESNUG 299 #12 ) Exporting From Synopsys dc_shell To EPIC PowerMill
> I am using EPIC's PowerMill to estimate power usage for netlists which I
> have created through Synopsys dc_shell. I would like to export the
> pre-layout parasitic values being calculated for each net from Synopsys's
> wire load models so that I can use them in the PowerMill run.
>
> I haven't been able to find a direct way of doing this, however. The
> closest "approved" method I've seen of getting the parasitic values out
> from the dc_shell is using the "write_parasitics" command, which generates
> an SPEF-format file. Unfortunately, the only format for a parasitics file
> which PowerMill accepts is DSPF, which is apparently incompatible.
>
> Is there an easy translation available for SPEF to DSPF, or is there a
> freeware/shareware/commercial product available which can do this? (Or
> any other solution to this problem?)
>
> - Kim Flowers
> TransLogic Technology, Inc.
From: Kim Flowers <kimf@translogic.com>
John, I just wanted to follow up on my post to ESNUG. One of my coworkers
ended up basically "grepping" (or using Perl) to extract out the capacitance
values from the SPEF netlist and construct a PowerMill script with
"add_node_capacitance" commands. This still doesn't address possible
resistance values, which can have a significant effect (depending on the
situation), but we're living with it right now.
- Kim Flowers
TransLogic Technology, Inc.
---- ---- ---- ---- ---- ---- ----
From: Chris Jacobs <chris.jacobs@analog.com>
John,
An alternative way to get pre-layout parasitic information from dc_shell is
through the "report_net" command.
Running this command with no options will list the capacitance for each
net, but it lumps the net capacitance and the gate capacitances together
(ie. C = Cwire + Cgate).
After this report is created, a simple script can be used to extract the cap
values. PowerMill can then accept the capacitance data in a variety of
ways. Two possible ways are:
A. Via a configuration command syntax of:
add_node_cap nodeName(s) capValue
B. Via standard SPICE netlist syntax of:
Cxx node1 node2 capValue
You then need to tell PowerMill to disable it's internal gate capacitance
calculations to prevent counting the gate capacitances twice (since DC
includes it in the report_net report). This can be done via the following
configuration command:
set_ckt_nogatecap value
This command affects the entire circuit. "value" can be set to one of:
1 = only gate capacitance will be set to 0.
2 = only gate overlap capacitance will be set to 0.
3 = both gate and overlap capacitance will be set to 0. <-- this is what
you want
- Chris Jacobs
Analog Devices, Inc. Wilmington, MA
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