( ESNUG 301 Item 6 ) --------------------------------------------- [10/15/98]
Subject: ( ESNUG 300 #4 ) VSS Only Supports VHDL'87; Not VHDL'93??! Huh?
> One of our customers popped up with a problem that was so outlandish I
> scarcely believed it. We delivered them a virtual component (aka "core")
> written in VHDL RTL version 1993. After a few days they came back
> and said their VSS system could not process it because *it only comprehends
> VHDL 1987*! They were given these systems on very favorable terms by
> Synopsys as an inducement to by other Synopsys software. The customer did
> not want to use a beta version of 1993 VSS that Synopsys has for the
> obvious reasons of nervousness, and they could not switch to Model Tech
> because they were too far down the road with the rest of their system in
> VSS. Is this for real? Did Synopsys really do that to them?!?!
>
> - Frederick Hinchliffe
> Technical Data Freeway Concord, MA
From: charles@efficient.com (Charles Shelor)
Yes, John,
Synopsys has refused to admit that IEEE-STD-1076 was updated in 1993. I even
have Synopsys paraphernalia from '96 with "Leader in VHDL techology". Ha!
Talk about misleading! It wasn't until this year; with the 1998.02 release;
that they support the "rising_edge" and "falling_edge" functions of the
original IEEE-STD-1164 package. That is 9 or 10 years after the standard
was approved!
Every time that I questioned/requested/demanded VHDL-93 support I received
responses such as:
o There is no feature in VHDL-93 that affects synthesis.
o You are the only user that has asked for 1993 support.
o Most of our users want faster simulation; not standards compliance.
I've even griped about lack of VHDL-93 support in this forum but didn't get
any support. Maybe I am the only user that writes test benches for VSS and
want to use the 'image attribute for printing the names of enumerated types.
I'm glad Fred wrote his letter. Now I know that there are at least two
people that find it unconsciousable that Synopsys would not be supporting a
standard that is already 5 years old.
- Charles F. Shelor
Efficient Networks Dallas, TX
---- ---- ---- ---- ---- ---- ----
From: Gregg Lahti~ <glahti@sedona.ch.intel.com>
John,
If I were in Mr. Hinchlifffe's shoes, I'd take the extra time to switch over
to Model Tech's modelsim.
I've had great success in using modelsim over using VSS. It's a much faster
tool, *much* better interface, with less language-related issues (such as
'93 and even syntax issues from '87). Modelsim also supports TCL/TK as a
built-in scripting language, which allows the user to do very complex
operations within the simulator.
The VSS interface is dismal, compile times are slow, & it's "understanding"
of the 1076 '87 LRM is horrid in a few key areas. Plus, Synopsys has no
true single-core co-simulator (VHDL/verilog) in comparison to modelsim. I
benched it last year and it still was slower in comparison to modelsim, plus
the VSS design viewer was an obvious bolt-on hack that still didn't give me
the flexibility I was able to get with modelsim. Synopsys should get a
wakeup call and fix VSS (or maybe buy a better simulator).
If I have to use a pure verilog simulator, it's VCS. If I need a VHDL
simulator or mixed language co-simulator, it's modelsim hands down.
My $.02 worth, and I am in no way affiliated with either company. I'm
just a really happy user of modelsim. ;^)
- Gregg D. Lahti
Intel
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