( ESNUG 302 Item 3 ) --------------------------------------------- [10/21/98]
From: "Charles Klaasen" <klaasen@natlab.research.philips.com>
Subject: How To Keep Logic0 Cells From Being Put On Unconnected Scan Ports?
Hello John,
Since the scan chains in my design are inserted 'outside' Synopsys, I
have unconnected (scan out) ports in my design. After a compile run, DC
connects these unconnected port to logic0. These logic0 cells cause
problems in the rest of the design flow. I can fix this with a simple
DC-script that removes these cells, but I was wondering if I can prevent
the inserting of the logic0's by with some variable or attribute???
- Charles E. Klaasen
Philips Semiconductors Eindhoven, The Netherlands
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