( ESNUG 302 Item 9 ) --------------------------------------------- [10/21/98]
From: [ Curious Minds ]
Subject: Seeking Lessons Learned -- Is VERA A Good Tool For Verification ?
Hi John,
I am looking for lessons learned from someone who has used VERA in the past.
Our full-chip Verification environment has Diag that issues commands to the
HW Abstract Layer which spawns Verilog simulation. The Verilog side then
forks, and execvp to execute a child process to run C simulation of C
Reference models.
During the course of C simulation, stimulus and responses around each module
are envelope-captured. The stimulus are sent to an IPC (Interprocess
Communication) FIFO to be applied to the Verilog counterpart. The responses
are sent to another IPC FIFO to be compared to that of the Verilog
counterpart. The Verilog and C sides are run in parallel and handshake thru
semaphore and shared memory.
I have two questions of which answers would help us in evaluating the tool.
First, what is your detailed lesson you learn from using VERA in your
environment. Any caveat and pitfall of the tool contrary to mktg claim ? How
does VERA stack up against Specman ?
Second, does anyone have a similar environment as ours and use VERA as a
cosimulator between C and Verilog sides successfully ? If yes, is there any
catch ? How are its RPC (Remote Procedural Call) and IPC ? Please keep
me anonymous because we're looking into a possible purchase of VERA.
- [ Curious Minds ]
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