( ESNUG 303 Item 10 ) --------------------------------------------- [11/4/98]
From: Vercelli Stefano <vercelli@sisun10.cselt.stet.it>
Subject: Help Needed In Translating Specific VHDL To Specific Verilog
Dear John,
I'm one of the lots of people who had to pass from VHDL to Verilog. In my
searching for documentation about verilog, I saw the web page with your
challenge. And so i thougth that maybe you can help me.
First, the environment I'm using. For VHDL, I use the Synopsys tools (now
with the 98.02 version); for Verilog, I have the Cadence Verilog-XL.
My problems are about some VHDL constructs (synthesizable!) that I'm not
succeeding to translate in Verilog. Maybe you know some "tricks" to solve
this problems. Here they are:
- Libraries: from what I read (from the online documentation) it seems
that in Verilog libraries there may be only components and primitives.
Can't I put in there a function or a procedure as I used to do in VHDL
packages?
- Sometimes I needed to define a signal whose range is defined by a
function. For example, I had a generic (let's call it SIZE), and I
needed to declare a signal whose dimension is defined by a function.
For example, if it had to be log2(SIZE), I defined a synthesizable
function (let's call it mylog2), and then I declared:
signal A: std_logic_vector(mylog2(SIZE)-1 downto 0)
I tried something like this in Verilog, but I didn't succeed. I defined
the parameter SIZE and the function mulog2, then I tried with
reg[mylog2(SIZE)-1:0] A;
But the compiler told me "Vector range must be a constant". I also
tried in defining an intermediate constant, that is:
parameter LOGSIZE = mylog2(SIZE)
But also here I had an error. Is there some solution to this problem?
- All my generical VHDL functions which accepted and returned unconstrained
std_logic_vector are no more possible here? Must I write a different
function for EACH dimension of the arrays?
Then something about the test benches. I used to have test benches whose
behavior was customizable through an external file (let's say this was a
command file that was read by the tester, and then it generated the stimuli
according to commands in the file). I read on manuals that in Verilog is
possible to WRITE on a file. But I found nothing about READING a file.
- Stefano Vercelli
CM/TM
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