( ESNUG 305 Item 4 ) --------------------------------------------- [11/18/98]
Subject: Use Cadence Or Avant!, But NOT Synopsys To Build Clock Trees
> I would like to build a clock tree into my design with Synopsys. Can
> someone tell me the commands to build it?
>
> - Manu
> Universita' degli Studi di Roma "Tor Vergata" Italy
From: Matt Guthaus <mguthaus@holabird.engin.umich.edu>
Generally people don't build a clock tree with Synopsys. This is done
better on the layout synthesis portion of design. You can back annotate
your design and look for problems/optimizations in Synopsys though.
Avant! has a program called Solar that I hear does well with clock tree
synthesis.
- Matt Guthaus
U Michigan
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From: jcooley@world.std.com (John Cooley)
I just wanted to agree with you, Matt, generally I hand design all my clock
trees because it's such a tricky thing and then use Synopsys to analyze it
afterwards relative to my design. The only gotcha is that in many cases you
only have front annotated numbers and skew can be difficult to estimate.
Usually, you can't use the individual buffer/inverter skews you find in the
data books because they're way too conservative. To get around this you
either have to do your own P&R or go back to your foundry and ask them to
analyze your hand designed clock tree for skew.
- John Cooley
the ESNUG guy
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From: Massimo Zucchini <zucchini@cadence.com>
John,
I also agree with you... Generally I design my clock-trees following these
steps:
a/ Insert a "place-holder" library macro foreach clock-tree at RTL level.
Investigate latency and skew issues foreach clock-tree.
b/ Write down an agreement with silicon vendor about clock-trees issues.
Depending on technology and layout-guy skill, today we can work with
very performant clock-trees...(assuming no latency issues, we can
deliver a clock-tree with a few ps. of skew (100,200 ps) and a latency
of 1-2 ps Typ. case for hundreds of fanout flops)
c/ From the RTL point of view, you can work with place-holder, paying
attention for buffer-insertion during synthesis ( clock-trees branches
must be clean) and using Synopsys "uncertainty" option if you like.
Again, working with "place-holder" lets you backannotate clock latency
directly on it rather that re-built a new netlist with all clock-trees
buffers inserted...
- Massimo Zucchini
Accent Vimercate (MI) Italy / Cadence
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From: iannuccelli@eln.uniroma2.it ( Manu )
I have try to build the automatic clock tree with CTS of Cadence (Cell
Ensemble) but this software have a bug. So I would like to build the clock
tree in Synopsys before.
- Manu
Universita' degli Studi di Roma "Tor Vergata" Italy
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