( ESNUG 305 Item 6 ) --------------------------------------------- [11/18/98]
From: Greg Brookshire <gbrookshire@peracom.com>
Subject: Synopsys Not Buffering Outputs Of Modules In Bottom-Up Approach
John,
We are using a bottom up synthesis approach for a chip that we are doing
with LSI. On our critical paths dc is leaving ***A drive parts on the
outputs when all the cells in the paths up to the output have C and D drive.
We are using
set_load load_of (lcbg10pv/BUFA/A) * 5.0 all_outputs();
which might be a little weak for nets that are enclosed by a much larger
wireload model, BUT even at the lowest compile level the last
incremental delay is the largest in the path because dc won't upgrade
from an A drive cell at the output! And these are paths that don't meet
their constraints at the lowest levels! Why won't dc increase the drive
strength of our output cells?
- Greg Brookshire
Peracom Cary, NC
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