( ESNUG 305 Item 10 ) -------------------------------------------- [11/18/98]
From: "Sean Atsatt" <seana@sierraimaging.com>
Subject: Does Anyone Have A VHDL "make" Program ?
Hi John.
At my last company we wrote a VHDL make tool that would automatically
generate a make file given the top level VHDL module and search paths for
the source code of lower level modules. Unfortunately I no longer have
access to that tool. The firmware engineers who work with us sneer (in a
friendly patronizing sort of way) at our clumsy manual make generation. We
use vmake with modeltech to generate a make file for an already built
design, but this still requires an initial user controlled compile. Does
anyone know of a good tool for automatically generating a VHDL make file?
We also auto generate our hierarchical VHDL code from a list of modules at
each level of hierarchy. The tool we use is hand rolled and a little clumsy
since we are too busy getting chips out to refine it. If someone has a
better one we would probably switch. Any ideas?
- Sean Atsatt
Sierra Imaging
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