( ESNUG 306 Item 1 ) ---------------------------------------------- [12/3/98]
From: "Brent Hayhoe" <hayhoe@nortelnetworks.com>
Subject: Synopsys Support Fatigue & Missing Altera FLEX Designware Components
Hi John,
Does anyone else get tired of reporting bugs to Synopsys? This is my
bugs-with-Synopsys scenario:
1. Oh, no, not another one. How on earth do I get around this?
2. After much farting around, decide that doing 'xyz' circumvents the bug.
3. Hmmm. Better report this to Synopsys.
4. Dear Synopsys, doing 'abc' results in an error. 'xyz' is a work-around.
5. Dear Brent, Please send your dc_shell scripts and VHDL source so that
we can replicate the problem.
6. Tar and compress files and send them off.
Reasonable I suppose, only my dc_shell environment is fairly contorted in
its set up, as are some of my VHDL libraries. I just know what their next
reply is going to be.
7. Dear Brent, Can't get your set-up to work. Have knocked up a script
to simulate what you're doing. Can you tell me what to set the
following dc_shell variables to? ...And these VHDL generics? Oh and
where are these constants set?
8. Spend another hour typing an Email explaining where everything is, etc.
9. Dear Brent, Still can't get it to work. Can you have a look at this
script and see what I need to do?
10. I really don't feel like it you know. And I've got a work around
anyway.
Now, I'm not knocking the Synopsys support guys. I think they've got a
tough job to do. My problem is that once I report a bug, I can see this
huge workload looming on the horizon and as I then have to work for Synopsys
Support in a sub-contract role! It's kind of embarrassing telling my boss
that I haven't finished what I'm supposed to be doing because I've been
typing Emails trying to sort out this bug that we've got a solution to
anyway. (Maybe Synopsys could pay my rates instead of Nortel whilst we
sort the bug out? Yea, I know: Dream on!)
So - a workaround - report it in ESNUG. Then everyone knows about it!
Here we go, latest bug...
Problem:
Whilst elaborating a VHDL design, the autolink links in a DB file of a
previously synthesized sub-design and just one of the Designware
components in this sub-design disappears.
Environment:
The design is targeted to an Altera 10K100 FPGA. The sub-design links
perfectly on its own. (It has HDL grouped process designs and Designware
designs within its DB file.) The part that is vanishing is an Altera
Designware part FLEX_ADD_MOD_6. There are other Altera Designware parts
but they link in OK.
Work-around:
Turn off the autolink around the elaborate command thusly:
auto_link_disable = "TRUE"
elaborate DESIGN_NAME_v -architecture DESIGN_ARCH_v \
-library DESIGN_LIB_v \
-update
auto_link_disable = "FALSE"
link
Now in my design flow, I synthesize each hierarchy level and save just that
level in its own DB file. As I do each level, all preceding levels are auto
linked in. So having solved the problem at this level, when I compile at
the next level up the Designware part disappears again. Fortunately my
elaborate is in a separate include file within my scripts and so once I
modify that, it's done for all levels. (Structured dc_shell scripting!
Wow! It's paid off at last!)
Any one else come across this before?
Any one else feel tired?
zzzz
zzzz
zzzz
zzzz
- Brent Hayhoe
Nortel Networks Harlow, Essex, U.K.
|
|
