( ESNUG 306 Item 3 ) ---------------------------------------------- [12/3/98]
From: eko@Aureal.com (Eugene Ko)
Subject: Bizarre, Mysterious 13% - 41% Area Increase With Aspec Libraries
John,
I'm using Aspec libraries, and Synopsys 1998.02 and 1998.08.
Even though I use no rams in my design, my design team shares a common setup
script, therefore a "ram.db" is added into everyone's (including my)
link_library and target_library.
Here's the problem: Although I don't have any rams in my design, the areas
increase about 15% to 40% if the Aspec RAMs are linked in!
My original design & environment was too big/complicated to send to the
Synopsys Support Center, so I replicated the problem using your simple,
public domain 8-bit counter from your "SNUG'95 Verilog Vs. VHDL Design
Contest". Attached are 3 scenarios that use that simple 8-bit counter and
Aspec libs.
First: No Aspec "ram.db" In Link_library Nor Target_library
link_library = {"sm222s.db"}
target_library = {"sm222s.db"}
read -f verilog counter8bit.v // a simple 8-bit counter
Total cell area: 430.00 // no ram.db in the link_library and
target_library
Second: Aspec "ram.db" That Contains Only One Specific Aspec RAM
link_library = {"sm222s.db", "ram.db"}
target_library = {"sm222s.db", "ram.db"}
read -f verilog counter8bit.v // same RTL, same constraints
Note: with each different specific Aspec ram in "ram.db", Synopsys puts
out different results! And my design DOES NOT use any RAMs!
Total cell area: 538.00 // one ram, cs1rwd128x1t16d1.lib, in ram.db
Total cell area: 492.00 // one ram, cs1rwd2048x16t16.lib, in ram.db
Total cell area: 488.00 // one ram, cs1rwd1280x8t16.lib, in ram.db
Total cell area: 554.00 // one ram, cs1rwd3840x21t16.lib, in ram.db
Total cell area: 549.00 // one ram, cs2rwd512x24t16.lib, in ram.db
Third: Aspec "ram.db" That Contains 1, 2, 3, 4 Specific Aspec RAMs In It
link_library = {"sm222s.db", "ram.db"}
target_library = {"sm222s.db", "ram.db"}
read -f verilog counter8bit.v // same RTL, same constraints
Total cell area: 492.00 // 1 ram in ram.db
Total cell area: 549.00 // 2 rams in ram.db
Total cell area: 595.00 // 3 rams in ram.db
Total cell area: 608.00 // 4 rams in ram.db
Again, remember, my design doesn't use any RAMs, yet my areas grow
if Aspec RAMs are in my link path.
I had submitted this bug to Synopsys two months ago. They re-produced the
problem but no workarounds for me so far. They talked to Aspec and looked
over their .lib source and report that it appears to be OK. When I tried
all three above scenarios using Cascade libraries, I didn't have any area
problems at all. (The main difference between Aspec libs and Cascade libs
is that Aspec uses table lookup timing model, Cascade however uses piecewise
linear model. I don't think this means anything, but it is a known
difference between the two libs.)
It's been two months. I can't wait any more. Did anyone run into the same
situation? Any solutions? Thanks.
- Eugene Ko
Aureal Semiconductor
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