( ESNUG 306 Item 4 ) ---------------------------------------------- [12/3/98]
From: [ Asterix, the Gaul ]
Subject: I'm Not Half As Starry-Eyed About Module Compiler As Synopsys Is !
Let's bounce the Module Compiler thread around again. I feel that Module
Compiler is worth talking about, I've been evaluating it and my experience
is not half as starry-eyed as the marketroids would have you believe.
Basically, it is a capable niche tool that fails totally to integrate with
Synopsys. I cannot see any medium-sized or non-specialist company making a
business case for it.
Reuse Wasn't Thought Out Well:
Module Compiler only considers reuse explicitly for structured expressions
using a MUX operator, as far as I can see. Module Compiler will not
spontaneously extract high-level structural information, such as the
similarity between an adder and a multiplier; this is disappointing.
I would have to manually restructure my design.
Restricted Input Format:
Module Compiler only considers combinational datapath expressions with
registers allowed only for pipelining. (For example, ordinary explicit
synchronous reset and load on registers is not possible!) Furthermore,
Module Compiler does not support any conditional constructs (other than
MUXing) -- so all IF and CASE statements would have to be totally
rewritten - not a good proposition.
Lack Of Integration With Design Compiler:
So where does this fit into the Design Compiler flow? The design engineer
would have to
a/ rigidly partition every register and conditional logic gate
out of their design into a separate module
b/ treat it as a blackbox inside Design Compiler
c/ characterise all loads and timing constraints to a script file
d/ haul the datapath into Module Compiler
e/ import the constraints (how?)
f/ optimise
g/ write Verilog output
h/ haul the datapath back into Design Compiler
i/ and treat it as a blackbox again for the purposes of optimization.
Would somebody like to estimate the complexity of a design required for
which the extra effort would break even compared to using the fastest DW
components and then fine-tuning Design Compiler?
I am not aware of the standard commercial pricing but I would strongly
expect that one seat of DesignWare would be far more generally useful
than Module Compiler.
On the positive side, the Module Compiler optimisation engine, for what
it is, is very promising. Synthetic cells are the way forward, to hide
spurious or marginal wireload-inspired 'optimizations' from the compiler,
while achieving genuine structural optimisations, such as an inverting
carry-chain, FAS cells, and various flavours of FFs.
But, can somebody tell me what Synopsys has been doing with it in the
two-and-a-half years since they bought SiArc? Tailoring it to CBA?
Disclaimer: please do not print unless I'm an utterly anonymous user of
Module Compiler. I don't want to be shot as a messanger by Synopsys.
A pseudonym might be Asterix, the Gaul.
- [ Asterix, the Gaul ]
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