( ESNUG 306 Item 11 ) --------------------------------------------- [12/3/98]
Subject: ( ESNUG 305 #15 ) We Got Results With Power Compiler/DesignPower
> I'm trying to use Power Compiler/DesignPower to reduce power in a design.
> All my gated-clocks are done manually, so I'm not using the "elaborate
> design -gate_clock" approach. When I try optimizing the design for power,
> it only gives a 1-2% decrease in power. From the documentation, I expected
> a 10-20% reduction in power... In one case, the power actually went up
> 1% after the final compile! I can give my test case or more info if it's
> needed. Thanks for any help.
>
> - Will Lentz
> Trimble
From: Zia Khan <zia.khan@intel.com>
John:
I have used Power Compiler and saw substantial power reduction. The results
of this work should be published in SNUG-98 this year. Briefly, one could
get 15% power reduction but at substantial area cost. By manipulating the
cost function one could limit area penalty for a lower power saving. For my
test cases, I was able to get 10% power reduction for 2% area penalty.
I also understand that Power Compiler now has a new option:
set_cost_priority -firm_area_limit
that could give user better control. I have not tried it yet so I can't
speak from experience.
- Zia Khan
Graphics Components Division
Intel Corp
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From: Hesham El-Adly <hesham@cae.ca>
Hi, John,
We've been getting fairly sizable power reductions using Power Compiler for
many of the blocks we've passed through the flow. Analyzing the results of
power optimization, I've noticed that much of the savings in power is due to
downsizing of drivers with relatively minor restructuring changes. Although
our ASICs are running at very high frequencies, we're targeting an advanced
ASIC technology with a rich library that leaves us room to "maneuver" to
optimize power.
We have also not seen any significant area increase during power optimization
but again this is mostly due to the richness of our ASIC library. (I'll
assume that switching power dominates the power in Will's design.) Success
with Power Compiler is linked to:
1) successful annotation of switching activity to the design
2) ASIC libraries which include multiple drive strengths and complex
combinational cells
3) timing not limiting power optimization
Switching Activity
------------------
For production work, we only extract switching activity from gate level
netlists. We are currently experimenting with applying switching activity
of only primary inputs, captured from RTL simulation, onto the gate level
netlist and using Power Compiler to propage the switching through the
design but we're unsure whether this will be successful and do not advise
it (at this time).
As the quality of power analysis is directly related to the success of
back-annotation of switching activity to the db, a procedure for checking
success of back-annotation should be a standard part of the methodology.
Steps to check coverage quality include;
-- Back-annotate switching activity
dc_shell> include designName_toggle.scr -quiet > designName_toggle.log
-- Report power per net to a log file
dc_shell> report_power -flat -net -nosplit > designName_toggle.rpt
-- Check the value of the switching activity attribute applied to each net
(write a little Perl script)
This is not an elegant solution - I'm hoping that Synopsys add a feature to
check coverage quality without forcing users to perform a complete power
analysis cycle.
ASIC Libraries
--------------
Libraries with multiple drive strengths, especially with more granularity in
drive strengths at the low end, are needed for large power gains. DC tends
to jump to the easy solution of using high drive buffers fairly early during
timing optimization. Power Compiler does a good job of resizing these
buffers during incremental compile with a power constraint.
Complex combinational cells are also important because Power Compiler tends
to enclose high switching nets within the complex cells resulting in a
reduction of capacitances of the enclosed nets.
Simply put, the richer the library, the better the results for timing and
power.
Timing Quality
--------------
Timing constraints take precedence over power constraints (and power
constraints take precendence over area constraints). If you have trouble
meeting timing with your current library, Power Compiler may not be able to
reduce power without structuring the gate level netlist differently.
You may be forced to apply switching activity of only the primary inputs of
the design to the elaborated db and use a power constraint during initial
compile to improve power. However, this still may not work if your timing
is very tight and your pushing the limits of your ASIC library.
It's not obvious to draw a conclusion why you haven't seen reduction in
power with Power Compiler but check whether the points I outlined make any
sense for your design and environment to start.
- Hesham El-Adly
CAE Electronics Ltd.
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