( ESNUG 308 Item 13 ) --------------------------------------------- [1/20/99]
From: Mike Klein <klein@chromatic.com>
Subject: Seeking Pointers On Super-High Performance Synthesis/P&R Approaches
John,
I'm on your ESNUG mail list and have been reading your great info source for
years now. I have a question, actually more a request for pointers,
regarding the use of Design Compiler on large, super-high performance
designs. I am hoping your readers can rattle something off to point me
in the right direction.
Our company (ATI Research, formerly Chromatic Research) is building higher
and higher performance processor-like chips, and we need to continue to
improve our methodology to support very high performance designs in the
future. Do you have any pointers to resources (articles, mags, people, ...)
that might give some reasonably detailed descriptions of how other groups
doing very large, very high performance chips are using Synopsys and their
favorite P&R tool to achieve good results? Throwing a large chunk of RTL
that produces a 100k gate netlist doesn't work. Example questions: How far
can you go with DC to produce near-fastest possible implementations? At
what point do you give up on DC entirely and do logic optimization by hand?
What's an optimal cell library for speed?
- Mike Klein
ATI Research, Inc. Sunnyvale, CA
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