( ESNUG 309 Item 1 ) ---------------------------------------------- [1/27/99]
Subject: ( ESNUG 308 #10 ) More Recent User Benchmarks Of Ambit vs. Synopsys
> I have used both. I am not an expert by any means. I used DC 3.1?
> and found it to be slow. I now use Ambit's BuildGates, it is fast in
> reading the design and in synthesis. May I suggest you call both of them
> and get an evaluation copy for your own consideration. IMHO, feature for
> feature, dollar for dollar Ambit comes out ahead over Synopsys.
>
> Well, they did before Cadence bought them. It remains to be seen if the
> value stays for Ambit, but that's a whole new thread.
>
> - Jerry English
> Planet C
>
> [ Editor's Note: This is *really* lame because he's comparing a current
> version of Ambit versus a 4.5 year old version of Synopsys. Lame!
> Does anyone have any current rev to current rev comparisons? - John ]
From: "Paul.Zimmer" <paul.zimmer@cerent.com>
John,
I read a sort-of Ambit "testimonial" a while back, and was disturbed by
two things:
1) The touted benefits were all PRE-ROUTE. Now, I have seen several
examples over the years of circuits that look larger/slower based
on wire-load pre-route estimates, were actually smaller/faster
when routed. I'm concerned that benchmarks based on pre-route
results will drive the vendors to produce netlist optimized for
the benchmarks, not real-life.
2) Even the pre-route data was dicey, because they didn't really prove
that the difference wasn't in the libraries and/or wire load tables.
The simple solution is to write out a netlist from each, then read
them both into a single tool (or try both tools) for timing
analysis.
This is still imperfect, because the wire-load tables can drive the
tools to different solutions, but at least it is more realistic than
just reciting the estimated cycle time from the tool itself.
I'd love to see comparisons of several decent-sized blocks synthesized
with both tools, then routed.
- Paul Zimmer
Cerent Corp.
---- ---- ---- ---- ---- ---- ----
From: Mike Dini <mdini@dinigroup.com>
John,
We are having trouble getting the attention of our local Cadence sales folk
to get a price and demo of Ambit. If you know, could you forward me the
email address of the VP of sales for Cadence so I may properly complain?
- Mike Dini
The Dini Group
---- ---- ---- ---- ---- ---- ----
From: Jay McDougal <jaym@hpcvcdt.cv.hp.com>
Hi John,
Concerning that 4.5 year old benchmark, I can do a little better, but not
the latest releases. Here are my notes from an Ambit vs. Design Compiler
evaluation I did almost a year ago:
Comparison of BuildGates(v2.0.4) and DesignCompiler(v1998.02):
This comparison includes some general comments, and specific result
comparisons for three different designs in terms of area, circuit
performance, and compile time. All compiles were performed on 100Mhz
HP C180 machines.
General:
BuildGates was fairly easy to use given experience with Design Compiler.
The methods of setting constraints, setting up libraries, and compiling
circuits are very similar. Also, the AMBIT documentation is written
to make the transition from Design Compiler easy. There were a few
things that were different enough to cause some difficulty such as
latch timing and target library specification.
Here is a short laundry list of items I noticed in my short time using
BuildGates.
- Report_timing is nearly interactive (a few seconds) even with 100K gates
- Capability to interrupt and re-enter compile process is great for
debugging timing constraints without waiting for long compiles to finish.
- Re-entrant compiles and control to run individual optimizations seems
like a great feature but I did not use it in my evaluation.
- All read, and write commands run much faster
- Applying constraints and library attributes is also much faster
- Ability to set timing constraints and get reports to hierarchical
boundaries instead of just pins/endpoints is very useful.
Comparisons
Circuit1:
Testcase with small portion of logic from address data path of a CPU,
about 5K gates.
BuildGates 2.0.4 DC 98.02
total compile time 40min 33min
area slack area slack
stats at finish of compile 265 0 292 0
Circuit2:
CPU core (50 to 60K gates) timing critical asking for 110Mhz with 78th
percentile wire load models. There are no path exceptions (false or
multicycle) and no latches.
BuildGates 2.0.4 DC 98.02
total compile time 13.3hrs 8.6hrs
area slack area slack
stats at finish of compile 3052 -0.32 3338 -0.37
In both cases the clk->clk paths all met the constraint but some
clk->out paths had small negative slacks.
Circuit3:
Complete CPU, about 100K gates. Asking for 110Mhz with 78th percentile
wire loads. Multiple path exceptions (both false and disabled paths)
as well as several hundred latches used to guarantee hold times to an
external RAM interface.
BuildGates 2.0.4 DC 98.02
total compile time 37hrs 29hrs
area slack area slack
stats at finish of compile 4900 -0.2 5395 -0.2
Both results are from top down compiles from the behavioral code.
Both circuits meet the clk->clk paths at 110Mhz (9.09ns period). With
the -0.2 slack in CLK->Q paths that end at heavily loaded outputs.
Summary
The results are very similar. BuildGates does show a consistent area
advantage of about 10% and a slightly longer compile time. It also
looks like the capacity of BuildGates may be more limited than that
of DC 98.02 as the compile time difference increased as the circuit gate
count went up.
I did not try any area sensitive designs where the timing was easily
achieved.
- Jay McDougal
Hewlett-Packard
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