( ESNUG 309 Item 10 ) --------------------------------------------- [1/27/99]
Subject: Is There An Altera ABEL To Verilog Translator Anywhere ?
> Is there an ABEL to Verilog translator out there anywhere ? I'm
> particularly interested in the state machine stuff.
>
> Also a question from a (relative) Verilog newbie coming from VHDL - How
> do you do parametrizable text macros. The OVILRM seems to say that this
> should work:
>
> `define my_add(x,y) x+y
>
> ... later in the code ...
>
> count = `my_add(count,1);
>
> But the Exemplar & Synplify tools don't accept it [neither does the vbpp
> pre-processor].
>
> - Rick
> Algorithmics Ltd.
From: Swapnajit Mittra <mittra@engr.sgi.com>
OK, first I would suggest that you should use
`define my_add(x,y) (x)+(y)
instead. Parametrized macros are a new feature to LRM2.0. I believe
Verilog-XL 2.X has implemented this feature. But all simulators may not be
ready yet. Here is an alternative. I am assuming you are using UNIX.
1. Instead of keeping the macros inside Verilog file (f1.v, say),
keep them in a separate file, say prep.m4 and in a slightly different
form: define(my_add,($1)+($2))
2. Run this at the command prompt: m4 prep.m4 f1.v
(m4 is a UNIX macro utility. It is usually kept in /bin/m4.)
If f1.v looks like
module mymodule;
reg a, b, c;
initial begin
c = my_add(a,b);
end
endmodule
You will get
module mymodule;
reg a, b, c;
initial begin
c = (a)+(b);
end
endmodule
You may have difficulty if you want to override existing macros, but I leave
that as an exercise for you ;-)
- Swapnajit Mittra
SGI
---- ---- ---- ---- ---- ---- ----
From: VITO <verilog@vito.com>
There is a pre-processor that someone implemented and presented a paper at
the 1996 IVC that I think handled this addition to the Verilog standard.
I lost my copy of the proceedings, and I can't recall the author's name.
There is another way to deal with this kind of code re-use that works
for all simulators, regardless of operating system: create an include
file, and redefine macros to act as arguments.
For example, the file "myadd.v" might be:
`DEST = `A + `B;
In the file where you want to use this:
`define DEST count
`define A count
`define B 1
`include "myadd.v"
This technique is more cumbersome, but is still useful if the include
file is extensive. Some simulators will give a warning about redefining
`A if you use the file with a different argument, but that does not
prevent the simulator from producing the right result.
Another technique I have tried is to define a macro instead of an
include file:
`define MYADD `A + `B
.... later ....
`define A count
`define B 1
count = `MYADD;
This does not work on many simulators because `MYADD is bound to "+" before
`A is bound to "count", so you get a syntax error on "count=+;".
- Mark
University of Wyoming
---- ---- ---- ---- ---- ---- ----
From: Swapnajit Mittra <mittra@engr.sgi.com>
> There is a pre-processor that someone implemented and presented a paper
> at the 1996 IVC that I think handled this addition to the Verilog
> standard. I lost my copy of the proceedings, and I can't recall
> the author's name.
That would be yours truly. I made the Version1.0 of this preprocessor,
which I called VIP, sometime during 1995. But I could not maintain it
or fix all the bugs. It was written in AWK, but I later figured out that
it could have been done using m4. If anybody is still interested, send
me a mail to "mittra@engr.sgi.com", I will be happy to send the tgz file.
- Swapnajit Mittra <mittra@engr.sgi.com>
SGI
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