( ESNUG 310 Item 4 ) ----------------------------------------------- [2/7/99]
Subject: ( ESNUG 309 #2 ) Speed Up This DC Script For Clock Domain Crossings
> I've got an existing design and I need to find all of the clock domain
> crossings in order to insert lockup latches for DFT. I could probably read
> through the code and find most of them, but I was hoping to automate it
> and catch all of them. I've written a dc_shell script that will do this,
> however the run time for this script is several days, even on an Ultra-10.
>
> Anybody have a faster script that can do the same thing? It can be a
> dc_shell script, perl or dc_perl or csh or whatever would be great. It
> just needs to be complete and fast(er).
>
> - Erik Trounce
> Nortel (Northern Telecom) Ottawa, Ontario, Canada
From: Ron Mehler <rmehler@dropzone.tamu.edu>
John,
Why not just let test compiler worry about that? Include the line:
set_scan_configuration -add_lockup true
and let it rip. I'm currently doing that on a 300k gate, 12 clock design.
It's working fine.
- Ron Mehler
Consultant
---- ---- ---- ---- ---- ---- ----
From: [ An AE In The Synopsys Support Center ]
John,
Below is a Design Compiler script which does what this user is looking for.
Users of PrimeTime might want to make a PT version instead, as PrimeTime's
efficient collections would allow it to run much faster.
This script could be written more straightforward, at the expense of more
runtime. However, using attributes on flops allows the use of a filter()
command to replace a lengthy foreach/if loop. Hopefully this is a cool
example of user-defined attributes, too!
You would use this script like so:
dc_shell>include cross_domain.scr
dc_shell>echo "The cross-domain flops in this design are" cross_domain "."
Here's my cross_domain.scr below:
clocks = find(clock)
ths_clk = "" > /dev/null
base_flop = "" > /dev/null
foreach(ths_clk, clocks) {
echo "Marking capturing data pins of domain" ths_clk "..."
data_pins = all_registers(-edge -clock ths_clk -data_pins) > /dev/null
if (data_pins != {}) {
set_attribute -quiet data_pins clock ths_clk -type string > /dev/null
}
dc_shell_status = 1
}
foreach(ths_clk, clocks) {
echo "Checking clock domain" ths_clk "as source of crossovers..."
out_pins = all_registers(-edge -clock ths_clk -output_pins) > /dev/null
if (out_pins != {}) {
echo " (determining total fanout)"
data_pins = all_fanout(-from out_pins -flat -endpoints_only) > /dev/null
echo " (making list of capture flops in other domains)"
set_attribute -quiet filter(data_pins, \
"(@clock > {}) && (@clock != ths_clk)") cross_domain true \
-type boolean > /dev/null
}
dc_shell_status = 1
}
cross_domain = {} > /dev/null
foreach(ths_clk, clocks) {
echo "Collecting cross-domain capturing pins from clock" ths_clk "..."
data_pins = all_registers(-edge -clock ths_clk -data_pins) > /dev/null
cross_domain = cross_domain + \
filter(data_pins, "@cross_domain == true") > /dev/null
remove_attribute -quiet data_pins clock > /dev/null
dc_shell_status = 1
}
Hope this helps!
- [ An AE In The Synopsys Support Center ]
---- ---- ---- ---- ---- ---- ----
From: Paul Carnaggio <Paul@syntest.com>
Dear John:
This question about finding Clock Domain Crossings went from ESNUG 309
Item 2 to one of the SynTest Engineers in Taiwan to L.-T. Wang ( President
of SynTest Technologies) to me. Isn't the net wonderful?!
Anyway, we have a Tool than can help this user called "TurboCheck-RTL."
SynTest Technologies of Sunnyvale, California specializes in DFT, Fault
Coverage Enhancements and Fault Simulations. You can visit our web page at
www.SynTest.com for company background and other technical information.
- Paul J. Carnaggio
SynTest Technologies, Inc. Pittsburgh, PA
---- ---- ---- ---- ---- ---- ----
From: William Liao <wliao@vadem.com>
Hi John,
On Synopsys's Solv-It website there is an article explaining how to do this.
I used the described method once, and it was fast for my design. Here are
the steps (using Erik's DC-shell variables):
/* group all paths into the default group */
group_path -default -to ckList
/* Mark all paths that start and end on the same clock as false paths,
and all those that start and end at ports */
foreach (ck, ckList) {
set_false_path -from find("clock", ck) -to find("clock", ck)
set_false_path -from find("clock", ck) -to all_outputs()
set_false_path -from all_inputs() -to find("clock", ck)
}
/* Now all remaining paths must cross clock domains */
report_timing
Regards,
- William Liao
Vadem
---- ---- ---- ---- ---- ---- ----
From: ehlers@sd.conexant.com (Steve Ehlers)
John,
Here's a script I put together based on an article on SolvNET that may
help this guy out.
/* Remove any existing false paths (we're trying to find clock crossers,
not mask them). */
reset_path -from all_clocks();
reset_path -to all_clocks();
/* Put all paths into a single path group. */
group_path -default -to all_clocks();
/* Ignore all normal paths (ones that start & end on the same clock). */
foreach ($clk, find(clock)) {
set_false_path -from find(clock, $clk) -to find(clock, $clk);
}
/* The SolvNET article recommends false-pathing to/from all
outputs/inputs, but that can mask clock crossing signals. If the
inputs and outputs are all properly constrained relative to their
respective clocks, only clock-crossing I/O's should show up in the
timing reports, making the next two set_false_path commands
unnecessary and undesirable.
*/
/*
set_false_path -from all_inputs() -to find(clock);
set_false_path -from find(clock) -to all_outputs();
*/
/* Show path details */
report_timing -path only -max_paths 100;
/* Shorter summary */
report_timing -path end -max_paths 100 -nosplit;
This should solve his problem...
- Steve Ehlers
Conexant Systems
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