( ESNUG 310 Item 10 ) ---------------------------------------------- [2/7/99]
Subject: ( ESNUG 309 #9 ) Trying To Model A Complex Cell In Library Compiler
> I to my final year project at Fachhochschule in Nueremberg/Germany. I want
> to create a new cell within the Synopsys Library Compiler.
>
> _____
> | |
> A----------------------|> |
> ____ _____ | |---------
> B---| |----| |--| FF |
> |mux | |latch| | |
> 0---|____| | | |_____|
> | | |
> sel__| | |
> ______________|> |
> |____ |
>
> Relationship between A and B
>
> A______--____
> B__--________
>
> I couldn't get the statetable right and have also problems with the pin
> describtion. It would be very kind of you, if you can give me some tips
> and tricks about this.
>
> - Klaus Gottschalk
> Fachhochschule Nueremberg, Germany
From: [ A Synopsys Library Compiler Guru ]
Hi John,
I have a statetable for the diagram Klaus has provided. However I am not
clear about a couple of things. First, I don't know, whether it's a zero
or the alphabet "O" on the mux. I have statetables for both the conditions.
Also he has not specified whether the latch is active high enable or active
low enable. I have assumed it as active high enable. For the pins, the
only additional thing that you need to do is have an additional internal
pin. This would be the pin which is the output of the latch. Let's call
it "I". Here is the statetable.
If the second input of mux is zero the table will look like this:
statetable ("A B sel G(latch gate)", "I Q") {
table : " - H/L L H :- -: H/L -,\
- - H H :- -: L -,\
- - - L :- -: N -,\
R - - - :H/L -: - H/L,\
~R - - - :- -: - N";
}
If the second input is "O" the table will look like this:
statetable ("O A B sel G(latch gate)", "I Q") {
table : " - - H/L L H :- -: H/L -,\
H/L - - H H :- -: H/L -,\
- - - - L :- -: N -,\
- R - - - :H/L -: - H/L,\
- ~R - - - :- -: - N";
}
Hope this helps in solving his problem.
- [ A Synopsys Library Compiler Guru ]
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