( ESNUG 311 Item 8 ) ---------------------------------------------- [2/18/99]
From: miller@symbol.com (Wayne Miller)
Subject: Inconsistent Port Maps Between 2 Levels Of VHDL Wasn't Flagged ?!?
Hi John,
This was bugging me last week, then Synopsys filed a STAR. I thought
I'd pass it along, and see if it is valid from an LRM standpoint.
Missing component outputs don't flag errors
I added an output to a lower level block using a schematic editor, but
I did not re-netlist at the top level. This resulted in inconsistent
port maps between the two levels of VHDL code. Neither vhdlan nor
-spc_elab generated even a warning. Is this legal? The code below
should make it clearer. (Note: If I omitted an input, then the parser
flags both missing ports.)
I can understand not mapping outputs in the instantiation, but
shouldn't the component declaration be checked?
-- Lower level
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
entity MYBLOCK is
Port ( IN1 : In STD_LOGIC;
IN2 : In STD_LOGIC;
IN3 : In STD_LOGIC;
OUT1 : Out STD_LOGIC;
OUT2 : Out STD_LOGIC;
OUT3 : Out STD_LOGIC );
end MYBLOCK;
architecture BEHAVIORAL of MYBLOCK is
begin
OUT1 <= IN1;
OUT2 <= IN2;
OUT3 <= IN3;
end BEHAVIORAL;
configuration CFG_MYBLOCK_BEHAVIORAL of MYBLOCK is
for BEHAVIORAL
end for;
end CFG_MYBLOCK_BEHAVIORAL;
-- Top level
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
library WORK;
entity TOP_MYBLOCK is
Port ( IN1 : In STD_LOGIC;
IN2 : In STD_LOGIC;
IN3 : In STD_LOGIC;
OUT1 : Out STD_LOGIC;
OUT2 : Out STD_LOGIC );
end TOP_MYBLOCK;
architecture SCHEMATIC of TOP_MYBLOCK is
component MYBLOCK
Port ( IN1 : In STD_LOGIC;
IN2 : In STD_LOGIC;
IN3 : In STD_LOGIC;
OUT1 : Out STD_LOGIC; -- !!!! NOTICE !!!! OUT3 is missing
OUT2 : Out STD_LOGIC );
end component;
begin
I1 : MYBLOCK
Port Map ( IN1=>IN1, IN2=>IN2, IN3=>IN3,
OUT1=>OUT1, OUT2=>OUT2 ); -- Again !!! OUT3 is missing
end SCHEMATIC;
configuration CFG_TOP_MYBLOCK_SCHEMATIC of TOP_MYBLOCK is
for SCHEMATIC
for I1: MYBLOCK
use configuration WORK.CFG_MYBLOCK_BEHAVIORAL;
end for;
end for;
end CFG_TOP_MYBLOCK_SCHEMATIC;
-- Variant
I also experimented with implicit port ordering:
I1 : MYBLOCK
Port Map ( IN1, IN2, IN3, OUT1, OUT2 );
This also did not generate any warnings, even though I'm mapping 5
signals to 6 ports.
Thanks for your help,
- Wayne Miller
Symbol Technologies, Inc.
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