( ESNUG 311 Item 11 ) --------------------------------------------- [2/18/99]
Subject: Unused Ports From Synthesis Causing Simulation Headaches
> After I synthesize a design, I'm re-simulating it as gate-level verilog.
> However, synopsys doesn't always use every port on a library component
> (e.g. Q and Q_BAR on a DFF). Verilog gives tons of warnings for this type
> of stuff. Is there a way to get rid of this?
>
> - Matt Guthaus
> University of Michigan
From: Igor Orlovsky <oia@javad.ru>
You can use +nowarnTFNPC option while verilog-xl simulation. Although you
may skip other port connection mismatches related to your hierarchical
modules.
- Igor Orlovsky
JAVAD Positioning Systems Moscow, Russia
---- ---- ---- ---- ---- ---- ----
From: david@rogoff.cnchost.com (David Rogoff)
The other way is to set VerilogOut_Show_Unconnected_Port = "TRUE" (I think I
got the name right). All your ports will be shown with no net. On the down
side I have seen this mess up some 3rd party timing estimators that didn't
understand the syntax.
- David Rogoff
---- ---- ---- ---- ---- ---- ----
From: "K. Y. Chan" <kychan@hintcorp.com>
It should be verilogout_show_unconnected_pins = true.
- K. Y. Chan
|
|
