( ESNUG 313 Item 4 ) ---------------------------------------------- [3/10/99]
Subject: ( ESNUG 308 #9 ) Forcing DC To Choose Better DesignWare Parts
> To force Synopsys to use a much faster "Booth-coded Wallace tree" or
> "wall" model, you have to do this:
>
> constant R0: resource :=0;
> attribute map_to_module of R0: constant is "DW02_mult";
> attribute implementation of R0: constant is "wall";
> attribute ops of R0: constant is "mul1";
>
> begin
>
> A <= B * C; -- pragma label mul1
>
> Ugly, isn't it? But it works. And it's fully debugged.
>
> - [ Kenny from South Park ]
From: Gzim Derti <gderti@intrinsix.com>
John,
If you want a way to perform DW component selection without mucking up your
RTL, this is a method that worked for me (plus a comment on how I've always
thought Synopsys should handle this using pragmas.)
The way that I did this on another job to increase speed on a part was
to first
1. Analyze and elaborate the design as normal.
2. Applied all of the constraints that I wanted.
3. compile -no_map
Once this is complete, you have a design which is in GTECH and unmapped
to gates.
4. report_resources
5. find the cell names of all of the adders in the design.
Let's say that an adder was names add_157 for instance. Then you perform...
set_implementation cla add_157 OR
set_implementation clf add_157 OR
set_implementation clf add* if you want to cover all the
adders in the current design.
This should leave you with a cla or clf representation for your adder, and
is much easier than the long winded way Synopsys wants you to do it with
attributes et. al.
I've been telling Synopsys for years that they need a: "-- pragma use" or
"// pragma use" option which can be coded in line and the compiler could
understand to you could enter:
c <= a + b; --pragma use clf
But talking to Synopsys about this is like talking to a wall...
- Gzim Derti
Intrinsix Rochester, NY
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