( ESNUG 314 Item 3 ) ---------------------------------------------- [3/17/99]
Subject: ( ESNUG 311 #8 ) Diff Port Maps w/ 2 Levels Of VHDL Wasn't Flagged?
> ... resulted in inconsistent VHDL port maps between the two levels of
> VHDL code. Neither vhdlan nor -spc_elab generated even a warning. Is
> this legal? ... I can understand not mapping outputs in the
> instantiation, but shouldn't the component declaration be checked?
>
> - Wayne Miller
> Symbol Technologies, Inc.
From: "Janick Bergeron" <janick@qualis.com>
John,
It is perfectly legal VHDL to have an unconnected output, either during
configuration (which he had) or during instantiation. It's similar to
not using the Qbar output on a Flip-flop. VSS is fine. A linting tool
could catch this as a warning. (VHDLLint? or DC's check_design command?)
- Janick Bergeron
Qualis Design
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From: Andrew Maccormack <andrewm@bristol.st.com>
John,
I couldn't find this in the LRM, but I know that it is the case. Unmapped
output ports are equivalent to mapping them to the "open" keyword. It's
like in C, where you can easily ignore the return value from a function...
It's not a Synopsys bug, it's a VHDL "feature"
- Andrew R MacCormack
STMicroelectronics
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