( ESNUG 314 Item 4 ) ---------------------------------------------- [3/17/99]
Subject: A Rose In Not A Rose Is Not A Rose -- Comparing Gate Counts In DC
> I have a synthesized a design using Synopsys. The area report gives me a
> cell area of 3245. Is this the gate count? If not, how can I extract the
> gate count from Synopsys?
>
> - Quek Kai-Hock
> National Technical University Singapore
From: david@rogoff.cnchost.com (David Rogoff)
It depends how the library was built. Here's what you do. Read in this
design:
module one_gate(q,a,b);
input a,b;
output q;
nand2 u0 (q,a,b);
// NOTE: may need to change nand2 to whatever your library calls it
endmodule
Read this into Synopsys and run an area report. This will be the area of
one gate in whatever units you library is defined.
- David Rogoff
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From: muzok@pacbell.net (muzo)
But one needs to be careful about the drive capability of the said nand.
There are usually more than one nand with different drives and different
equivalent gate sizes. You need to chose the one gate equivalent which
is usually the smallest.
- Muzo
Kal Consulting
---- ---- ---- ---- ---- ---- ----
From: tcoonan@mindspring.com (Thomas A. Coonan)
Right.
My 0.35 library has the ND2 cell (2-input NAND) listed with an area of 54.
In the same vendor's 0.25 library, the same cell reports as 27 units (this
vendor lists sq-um). Therefore, for my particular libraries, I divide
'area' by either 54 or 27 respectively. Your design should almost surely
have either a 2-input NAND or NOR in it, so hopefully you don't need to do
the benchmark circuit -- just look through your report_area output (you'll
surely see even smaller Inverters or Buffers cell, so make sure its the
low-drive NAND/NOR and not an inverter).
- Thomas A. Coonan
---- ---- ---- ---- ---- ---- ----
From: Jason Doege <jdoege@centtech.com>
Other are pointing you at equivalent gate count, a derived value based on
area. This, however, is not what you asked for. To find out how many
gates you have in your design, using dc_shell:
count = 0
cell_list = find (cell -hierarchy, "*")
foreach (cells, cell_list){
count=count+1
}
echo "The total number of instances in this design = " count
This is from "Logic Synthesis Using Synopsys 2nd ed." By Pran Kurup and
Tahaer Abbasi, a very worthwhile book. That script will include flops
and latches in the gate count. This book has other scripts that give a
better report showing counts of gates, flops and latches.
- Jason Doege
Centaur Technology
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