( ESNUG 315 Item 3 ) ---------------------------------------------- [3/24/99]
From: david_johnson@paging.mot.com (David Johnson)
Subject: A Workaround Script For The Design Compiler check_design Bug
John,
I definitely get some useful information from ESNUG (and I appreciate the
humor too!) so I'd like to contribute something. I ran into a problem
with Design Compiler check_design. For hierarchical designs, check_design
does not warn about an output port being not connected _external_ to the
cell if the port is connected _internally_ to the cell to an output and
an input. See STAR 69047 (acknowledged as a BUG).
Now Verilint or other similar tools might catch this problem, but for
designers that rely only on Design Compiler for check_design, I have
a work-around script that might help them until Synopsys fixes the bug.
echo "exeternal pin connection report for " + _design >
_external_pin_report_file
echo "---------------------------" >> _external_pin_report_file
echo "" >> _external_pin_report_file
current_design _design
_hier_cells = {}
if (_recursive == 1) {
_hier_cells = filter(find(-hier,cell, "*"),"@is_hierarchical == true") >
/dev/null
} else {
_hier_cells = filter(find(cell, "*"),"@is_hierarchical == true") >
/dev/null
}
foreach(_cell, _hier_cells) {
echo "checking CELL " + _cell >> _external_pin_report_file
_pin_errors = 0
foreach(_pin, find(pin, _cell + "/" + "*") {
all_connected(_pin)
if (dc_shell_status == {}) {
get_attribute _pin pin_direction
foreach (_direction, dc_shell_status) { }
echo " (WARNING) no external connection for" _direction "port"
_pin >> _external_pin_report_file
_pin_errors = 1
}
}
if (_pin_errors == 0) {
echo " all pins connected externally" >> _external_pin_report_file
}
echo "" >> _external_pin_report_file
}
User specified variables:
_design = top-level design name
_recursive = 1: run check on all cells recursively through the hierarchy
= 0: top level cells only
_external_pin_report_file = report file name
examples:
dc_shell> _design = cpu
dc_shell> _external_pin_report_file = ../report/cpu.external_pins.rpt
dc_shell> _recursive = 0
dc_shell> include "check_design_one_level.scr"
Use Synopsys Design Compiler 1998.08 (possibly earlier versions as well)
- Dave Johnson
Motorola
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