( ESNUG 315 Item 7 ) ---------------------------------------------- [3/24/99]
Subject: ( ESNUG 313 #8 ) I Can't Confirm The So-called hdlin_use_cin "Bug"
> Way back in ESNUG 264 we learned about a neat switch in Synopsys for
> optomizing logic. The switch was "hdlin_use_cin = true" which allows you
> to use the carry in input of an adder if you are doing an "a + b + 1"
> operation. (Why Synopsys doesn't do this automatically I have no idea....)
> This saves you an entire adder in your design, and can really speed up
> your arithmatic.
>
> However, recently a bug has surfaced. If you have any logic associated
> with the "a" and "b" inputs which moves bits in the buss around (like a
> simple shift to multiply by 2) then that logic gets "eaten" by the adder,
> and you wind up with something that doesn't add up. I've actually gone
> to the point of removing this variable from all of my .synopsys_dc.setup
> files because of this.
>
> - [ Kenny from South Park ]
From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
John -
I read the post about using the switch hdlin_use_cin = true. Could you ask
[ Kenny from South Park ] to post an example design that shows a post-
synthesis failure?
I've been teaching people in the Synopsys Advanced Verilog classes for the
past 2 years to use this switch and to add it to their .synopsys_dc.setup
file, because of the remarkable improvement that this switch causes to the
size and speed of arithmetic logic designs. If this switch truly does cause
a problem, Syonpsys should be notified and I owe a lot of former students
an update e-mail.
Looking at Kenny's description, I tried to recreate a failure but without
success. All of my pre-synthesis designs match my post-synthesis designs. I
am not trying to cast doubt or in any way embarrass Kenny for raising this
issue, but frequently when multiplying by a fixed number, and in particular
when multiplying by a power of two (or shifting as Kenny has suggested),
the compiled design often looks strange because no additional hardware is
generated, but the input wires have shifted to account for fixed
multiplication. I don't know if that is what Kenny means by "logic gets
eaten" or not.
Below I have copied the experiment files that I ran along with the Synopsys
synthesis script that I used to generate the gate-level files.
My DC script:
hdlin_use_cin = true
read -f verilog addert2_hdlin.v
current_design = addert2_hdlin
compile
ungroup -all -flatten
write -f verilog -hier -o addert2_hdlin.vg
hdlin_use_cin = false
read -f verilog addert2_nohdlin.v
current_design = addert2_nohdlin
compile
ungroup -all -flatten
write -f verilog -hier -o addert2_nohdlin.vg
NOTE: The next two files are identical except for the module names. This
made the synthesis scripting and the testbench easier to generate.
module addert2_hdlin (co1, sum1, co2, sum2, a, b, ci);
output [7:0] sum1, sum2;
output co1, co2;
input [7:0] a, b;
input ci;
assign {co1, sum1} = a + b + ci;
assign {co2, sum2} = (a*2) + (2*b) + ci;
endmodule
module addert2_nohdlin (co1, sum1, co2, sum2, a, b, ci);
output [7:0] sum1, sum2;
output co1, co2;
input [7:0] a, b;
input ci;
assign {co1, sum1} = a + b + ci;
assign {co2, sum2} = (a*2) + (2*b) + ci;
endmodule
I ran the RTL designs against gate-level models after synthesis with 10,000
random input vectors. Compared all RTL & gate-level outputs. No failures.
- Cliff Cummings
Sunburst Design Beaverton, OR
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