( ESNUG 316 Item 11 ) ---------------------------------------------- [4/8/99]
Subject: Back-annotation On Verilog-XL Is Very Slow Compared To VCS
> Has anyone found that for a given testbench, back-annotation an sdf file
> for a gate-level simulation in Verilog-XL takes MUCH longer than it does
> with VCS? (3-4 hours vs. 4 minutes respectively for one of my test
> benches). What's the reason for this? How does each tool perform back-
> annotation?
>
> At first, I thought that VCS wasn't performing back-annotation, but after
> throwing some deliberate "errors" in the netlist at VCS, it detected them.
>
> I changed the module type from a low-drive gate to a high-drive gate. I
> changed the instance name to something non-existent in the sdf file. Both
> changes were flagged by VCS. Can anyone offer any explanations?
>
> I'm using VCS v5.0 and Verilog v2.6.
>
> - Alfred Cheung
> Nortel Networks Ottawa, Ontario
From: Ashutosh Varma <ashu@axiscorp.com>
You may be using the compiled SDF feature of VCS, which may be default
now. In that case, the SDF file is read at compile time rather than at
run time.
- Ashutosh Varma
Axis Systems Sunnyvale, CA
---- ---- ---- ---- ---- ---- ----
From: Petter Gustad <pegu@dolphinics.no>
Also: Verilog-XL usually uses more memory than VCS. Maybe your XL
simulation exceed the amount of physical memory in your machine and
the VCS does not?
- Petter Gustad
Dolphinics Norway
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