( ESNUG 318 Item 10 ) -------------------------------------------- [5/21/99]
From: John Patty <jrpatty@rtp.ericsson.se>
Subject: Can't Get DC To Remove Tied-off/'Dead' Flip-flops From My Design
Dear John,
I am having difficulty getting Design Compiler to remove flip-flops that
are tied off to a useless state. The specific example I am looking at is
a d-type flip-flop with an asynchronous clear. It's D input is tied to
'0'. The CLR input comes from other logic. So only 0's can be clocked in
to this flop, and it can be cleared to set it to '0'. There is no way to
set it to '1'.
---------
'0' ----| D Q |---- Output
| |
CLK ----|> |
Reset -----------| RST |
---------
It seems to me that Design Compiler should optimize this dead flip-flop
away and replace it with a tie-off to '0', which should then allow
logic on the output side of the logic to be further optimized away.
However, in my experience, this is not the case. The commands: compile,
compile -boundary, and compile -in_place will not do what I want it to
do. This configuration is not exactly the same as a tie-off since the
flop could possibly power on in the '1' state, but I don't think this is
a good enough reason not to allow the above optimization. Has anyone had
any success with this, or know a better reason why this should not be
optimized away?
- John Patty
Ericsson Research Triangle Park, NC
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