( ESNUG 320 Item 5 ) ---------------------------------------------- [6/2/99]
Subject: Synplicity's Latest Version Of Synplify Is Now Much Pickier!
> I recently upgraded to version 5.1.2 of Synplify and was horrified to find
> the number of warnings issued for my designs have exploded!
>
> I regularly put into the process sensitivity list only the signals that
> are used in decisions, such as "if" or "case" statements. The previous
> version of Synplify was quite happy with that. Now it wants every signal,
> even those only used to assign a value, in the sensitivity list. For
> example, in x <= y, y is now needed in the sensitivity list, otherwise
> I get a warning.
>
> Was I out to lunch in my previous assumption that only decision-making
> signals should be in the sensitivity list?
>
> - Jamie Sanderson
> Nortel Networks Canada
From: Jan Decaluwe <jand@easics.be>
If your process describes combinatorial logic, yes. Suppose that at a given
time, *only* signal y changes value. You still expect to see the effect of
this change on the outputs, right? Therefore, y should be in the
sensitivity list. If you don't put it there, the RTL will have more "state"
and thus a different behavior than the synthesized logic. Therefore, the
warnings are certainly appropriate. Note: however that if you use the
clocked process paradigm, only clock and reset need to be in the sensitivity
list.
- Jan Decaluwe
Easics Leuven, BELGIUM
---- ---- ---- ---- ---- ---- ----
From: Renaud Pacalet <pacalet@enst.fr>
Think hardware and hardware only. A process is either a 1) synchronous
one (synthetizes with DFFs) and must be sensitive to clock only (and reset
signal if it is an asynchronous one) or 2) a combinational one and must
be sensitive to all signals that are entries of the corresponding
*hardware* glue logic. Examples:
process(CK)
begin
if (CK = '1') then
S <= A + B;
end if;
end process;
is a synchronous process without reset. It synthesizes a DFF register for
S and an adder.
process(CK, RST)
begin
if (RST = '0') then
S <= (others => '0');
elsif (CK = '1') and (CK'event) then
S <= A + B;
end if;
end process;
is the same but with an active low asynchronous reset on the register.
process(I0, I1, I2, STATE)
begin
case STATE is
when S0 => NEXT_STATE <= S1;
Z <= I0 and I1;
when S1 => if (I0 = '1') then
NEXT_STATE <= S2;
elsif (I1 = '1') then
NEXT_STATE <= S3;
else
NEXT_STATE <= S1;
end if;
Z <= I2 xor I0;
when S2 => if (I1 = '0') then
NEXT_STATE <= S0;
else
NEXT_STATE <= S2;
end if;
Z <= '0';
when S3 => NEXT_STATE <= S2;
Z <= '1';
end case;
end process;
is a combinational process. It must be sensitive to all entries of the
equivalent glue logic part. STATE is used for decisions only, I0 and I1
are used for decisions and assignments, I2 is used for assignments only.
All are absolutely needed in the sensitivity list. Another constraint is
that all outputs must receive a value in every situation. If you don't
respect this constraints you'll synthesize something that has a different
behavior than your simulations. In fact, if you don't respect this
constraints you are using VHDL to describe something that is not hardware
at all. A good synthesizer complains, a bad one does anything.
- Renaud Pacalet
ENST / COMELEC Paris, France
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