( ESNUG 322 Item 5 ) ---------------------------------------------- [6/15/99]
Subject: ( ESNUG 321 #10 ) A Module Compiler Trick That Synopsys AE's Hide
> I have been given the task of evaluating Module Compiler. After cruising
> along the learning curve quite well, I came to a roadblock. The ALU
> datapath I was implementing as a test case had the use of intermediate
> carry bits from the 32-bit adder. I have yet to find in the documentation
> how one gets access to these bits or if it is even possible. Any help
> from ESNUG would be appreciated.
>
> - Barry Williams
> Rockwell Avionics
From: [ Casper, The Friendly Ghost ]
John,
Please keep me anon, but the Synopsys AE's are always trying to keep people
from using a very powerful feature of Module Compiler -- it used to be in
the documentation, but they even took it out of there!
For carry save arrays, there is a way to access the carry and sum terms
prior to the final add. This is great if you want to control the pipelining
yourself, instead of hoping that MC finds the right place for your regs.
The example below does a simple multiply, but registers the values prior
to the the final add.
module TEST (Z, X, Y);
input [w-1:0] X, Y;
output [2*w-1:0] Z;
wire [2*w-1:0] PRODS, PRODC;
directive local (carrysave="convert", pipeline="off");
wire [w*2-1:0] PROD = X*Y;
csconvert(PRODS, PRODC, PROD);
PRODS_reg = sreg(PRODS);
PRODC_reg = sreg(PRODC);
Z = ACC0+ACC1; //Adding the two terms together, or to another
//signal brings um back together.
endmodule
You can use this to create superfast accumulators or if the Multiplier feeds
other adders you can often save a carry propagate add.
To be fair to the Synopsys AE's, this approach has 2 drawbacks:
1. Hard to verify
2. if you try to do any logic on these outputs seperately, you can
really screw yourself (like trying to check if they are zero...)
At my last company we used this feature to get great results!
- [ Casper, The Friendly Ghost ]
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