( ESNUG 322 Item 12 ) --------------------------------------------- [6/15/99]
Subject: ( ESNUG 320 #11 ) Designing High Speed FPGA Multipliers
> I was wondering if anyone can refer me to some information about designing
> an 8-bit by 4-bit unsigned multiplier and an 8-bit by 4-bit signed
> multiplier that will perform at high clock speeds and have efficient usage
> of CLBs on the Xilinx Virtex FPGA.
>
> - Allen Tung
> Visicom Labs San Diego, CA
From: [ A Synopsys FPGA CAE ]
John,
With version 3.2 of FPGA Compiler II and FPGA Express, you can get improved
FPGA architecture-specific multiplier implementations for Virtex and XC4000
devices. See http://www.synopsys.com/fpga/ for more info and software
downloads.
- [ A Synopsys FPGA CAE ]
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