( ESNUG 322 Item 13 ) --------------------------------------------- [6/15/99]
Subject: ( ESNUG 317 #6 ) Propagate_constants Doesn't Work Like You Think
> The propagate_constraints command has already made my life much easier
> by simplifying the application of constraints in a design hierarchy.
> Constraints can be applied at a lower level of the hierarchy and then
> propagated to the top level with the propagate_constraints command.
> Propagate_constraints works as advertised and only as advertised. So be
> sure to read the documentation. I had a case in which I segmented timing
> paths using input and output delays on an internal pin. These constraints
> are not propagated (yet--track STAR 69625). I was able to get around this
> problem thanks to the the new "-through" option for timing exceptions.
>
> - Greg Mann
> Ford Microelectronics Colorado Springs, CO
From: London Jin <londonj@eng.adaptec.com>
John,
I learned from ESNUG 317 that propagate_constraints made your life much
easier. You may be able to shed some light on this. I tried it, and
wanted to see how it works, and all I got at top-level were clock specs
(which is trivial). I expected to see set_input_delay & set_output_delay,
too. (Are these realistic expectations?) The following is what I did.
read top.db
characterize u_bac
current_design bac_test_1
write_script -format dcsh > bac.scr
write -f db -hier -o bac.db
remove_design -d
read -f verilog top.v
remove_design bac_test_1
read bac.db
current_design top
link
current_design bac_test_1
include bac.scr
current_design top
propagate_constraints -design bac_test_1 -all
write_script -format dcsh > top.scr
Any hint is greatly appreciated.
- London Jin
Adaptec
---- ---- ---- ---- ---- ---- ----
From: gmann@ford.com (Greg Mann)
Hi London,
I was a little vague in my comments in ESNUG 317 which probably lead to your
confusion. propagate_constraints doesn't propagate set_input_delay or
set_output_delay statements no matter what options are used, but is used to
propagate exceptions such as set_false_path, set_multicycle_path,
set_clock_gating_check etc. (See the Synopsys On-Line Docs for a
comprehensive list).
The problem that was solved by the -through option solved was a case in
which I needed to apply the constraint:
set_false_path -through find(pin,U1/A) -to find(cell,out_reg)
The version of Design Compiler I was using when I wrote the original
constraints didn't support the -through option, so the path had to first be
segmented using set_input/output_delay statements followed by a
set_false_path constraint as shown below.
/* Segment the path */
set_input_delay 5 -clock CLK find(pin,U1/A)
set_output_delay 5 -clock CLK find(pin,U1/A)
/* Apply false path exception */
set_false_path -from find(pin,U1/A) -to find(cell,out_reg)
Since propagate constraints doesn't yet support set_input_delay and
set_output_delay, it wouldn't propagate my constraints correctly. But when
I changed my constraint to a simple set_false_path command with
the -through option, propagate_constraints worked correctly.
- Greg Mann
Ford Microelectronics Colorado Springs, CO
|
|
