( ESNUG 323 Item 2 ) ---------------------------------------------- [7/22/99]
Subject: EDA Product Keyword Counts & TeraForm Isn't A Datapath Compiler
> THE EMPEROR HAS NO CLOTHES? For this DAC Trip Report, I had 77 engineers
> respond. And, as a rough cut on how engineers comparitively saw all these
> new physical tools, I did a quick keyword count.
>
> Magma 'Blast Fusion' 103
> Avant! Jupiter 48
> Cadence Ambit PKS/Envisia 26
> Monterey Dolphin 22
> Synopsys 'Chip Architect' 9
> Tera Systems TeraForm 5
> Sapphire FormIT/NoiseIT/PowerIT 3
> Silicon Perspective 'First Encounter' 3
> Aristo 'IC Wizard' 2
>
> Mentally checking the data, it made sense. The between-synth-and-P&R
> tools like TeraForm, Sapphire, Encounter, and IC Wizard weren't big news
> items compared to the Magma/Monterey/Avant! stories. What surprised me
> was that so few engineers made reference to Chip Architect from Synopsys.
> Roughly a 10X difference between it and Magma.
From: Richard Gordon <rgordon@terasystems.com>
John,
(I apologize that I didn't direct my *huge* marketing staff to contact all
of our customers and DAC prospects and urge them to respond to your DAC
User Survey. I know it's a little late, but since Tera shows up 9 times
in this email, could you pump up our keyword count? <Grin>.)
I wish to clarify the misperception that our TeraForm product is squeezed
in-between synthesis and place-and-route, like X-IT, Encounter, & IC Wizard.
Since an earlier ESNUG thread (ESNUG 279, 280, 281) successfully helped to
position Tera Systems incorrectly as a DATAPATH company, which we are NOT,
perhaps you will grant me license to set the record straight -- Tera
delivers systems for RTL _design planning_.
Our TeraForm RTL design planning product is an interactive FRONT-END system
that is used PRIOR to gate-level logic synthesis. TeraForm partitions the
RTL logical hierarchy into a physical hierarchy, designed to produce an
efficient physical implementation, and constructs a detailed, full-chip
floorplan (what Gary Smith calls a silicon virtual prototype). The
floorplan gives TeraForm wiring parasitics that are used for accurate RTL
timing analyses.
TeraForm reads in RTL, works on it, and outputs RTL.
The TeraForm'ed RTL, wiring parasitics, timing, and floorplan data are
emitted as constraints for gate-level synthesis and place-and-route tools,
giving them a better starting point and accelerating timing convergence
at high clock speeds.
Hope your back is fully recovered!
- Richard Gordon, Executive VP
Tera Systems, Inc. Campbell, CA
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