( ESNUG 323 Item 3 ) ---------------------------------------------- [7/22/99]
Subject: Gotchas If You Let Avanti Apollo P&R Restitch Your Scan Chains
> "I ran into a guy named Al Crouch at the Mentor's Design-For-Test
> booth. He clued me in on a bunch of scan chain problems, so I feel
> obliged to put in a plug for his book "DFT for Digital IC's and
> Embedded Core Systems". Al definitely had a strong opinion that
> Synopsys' Test Compiler is an inferior product. (Probably why
> Mentor Graphics hosted him at their booth).
>
> Here are the scan chain gotchas he told me to watch for if we allow
> Avanti Apollo P&R to restitch the scan chain:
>
> 1) Apollo will not recognize separate clock domains when it
> restitches. It simply routes from flop to nearest flop without
> regard to the clock. To get around this you need to put each
> clock domain on a separate scan chain and explicitly tell Apollo
> which registers are on which chain. (I think that putting each
> chain on it's own enable facilitates this.)
>
> 2) We cannot allow Synopsys to put buffers along the chain. Apollo
> ignores them, routes flop to flop, and leaves the buffers and
> inverters hanging.
>
> 3) Apollo does not have any sense of timing, so when it restitches
> and routes to the flop next door it could cause hold violations.
> Al mentioned a design he had with about 5000 flops. Apollo
> introduced 3000 hold violations.
>
> Email Al_Crouch@prodigy.net w/ questions. He was a really nice guy."
>
> - an anon engineer
From: [ An Ounce Of Prevention ]
John,
I snipped this part of your trip report out and forwarded it to our P&R
guy. He was pleased to get these warnings ahead of time. Thanx!
Anon if you print this.
- [ An Ounce Of Prevention ]
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