( ESNUG 323 Item 8 ) ---------------------------------------------- [7/22/99]
Subject: Monterey Dolphin Put 800 kgates Into 12,000 Microns, Not 1,200
> "Monterey: SUITE DEMO: "Dolphin"
>
> Simultaneous P&R, timing, logic optimization. ... Scan chain
> reordering to reduce congestion. Recommend: ATPG after P&R. Largest
> example: 280k cells, 800k gates, 1200 microns on a side1. 1-2 days
> run time on a multiprocessor (Sun 6500, 24 processor, 24 GByte).
> Input: .lib, netlist, lef, Synopsys timing constraints. In-memory
> data model, checkpoint capability."
>
> - an anon engineer
From: Simon Favre <simon@mondes.com>
John,
Whew! what a trip report! One minor correction: In the Monterey Design
Systems "Dolphin" section, our largest example was 12000 microns on a side,
not 1200. If we could put 800K gates in an area 1.2 millimeters on a side,
WE would be buying Cadence and Avant! The "Dolphin" section of your report
sounds a lot like my suite demo speech condensed...
Thanks for the additional perspective on DAC.
- Simon Favre
Monterey Design Systems (& former Synopsys lib manager at LSI Logic)
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