( ESNUG 323 Item 10 ) --------------------------------------------- [7/22/99]
Subject: CAE Plus Inc. Rebuts How Their Tool's Function Was Explained
> Looking bass ackwards at this religious C-to-Verilog mindset, CAE Plus
> ( http://www.cae-plus.com ) offers to 1000X speed up your Verilog sim by
> translating your Verilog to C, have you debug and run 1000X faster in C,
> and then when everything's done, you translate your C back to Verilog
> again for synthesis to gates. Watch out VCS & NC-Verilog!
From: Sandhya Shardanand <sandhya@cae-plus.com>
John, thanks for mentioning us in your DAC report and we appreciate your
left-handed compliment. However...
We want to clarify what appears to be some misinterpretation of how our
tools work. We only go from logic-synthesizable Verilog into RTL-accurate
C (our trademarked term for this is "RTL-C").
Most C verification companies advocate designing in C and verifying in C,
which does not allow reuse of existing Verilog models and is a major
change to the HDL design methodology. With our new tool Afterburner, we
are letting designers continue to design in Verilog and perform high-speed
verification in C. Any design modifications are made to the Verilog,
therefore there is no need to translate the C back to Verilog.
I hope that you will post the necessary correction on ESNUG.
Just for your information, here is a brief description of our three tools
and how they work together :
1) Our design capture product, ArchGen, captures the design in a
behavioral-level, graphical event flow language, while data operations
continue to the coded in Verilog. ArchGen then synthesizes the
ArchGen model from the behavioral level into both the RTL-C and the
RTL-Verilog representations. This assures consistency between the C
and the RTL.
2) Our new verification product, Afterburner, generates RTL-C from
existing logic-synthesizable RTL-Verilog and enables the designers
to continue to capture at RTL level in Verilog but provide higher
speed C verification.
3) Our C integration tool, ASVP Builder, creates a standalone C simulator
and automates the integration of one or multiple RTL-C models with
each other and other embedded-software development tools, simulators,
test benches, co-verification environments, and/or user written C
programs or hardware models to help users put together "Application
Specific Virtual Prototypes" for system-level verification.
Our approach is an evolutionary one rather than a revolutionary one such as
those advocated by other C companies.
- Sandhya Shardanand, Marketing Manager
CAE Plus Inc.
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