( ESNUG 324 Item 8 ) ---------------------------------------------- [8/04/99]
Subject: Some Misguided Comments Concerning Asynchronous Circuit Design
> "Steve Nowick of Columbia U. presented an overview of asynchronous
> circuits. He kept saying words like 'difficult' and 'complicated'
> and 'hazards'. Their experimental burst mode FSM design tools can
> synthesize about 15 gates. (Yes, it's that small. 15.) Ken Yun of
> UC San Diego talked about timed asynchronous circuits. These are
> circuits whose timing properties are very carefully analyzed. They
> can run very fast, but there are no tools for them. Overall, the two
> made asynchronous circuits seem difficult. Alex Kondratyev, U. of
> Newcastle, mentioned that more concurrency does not mean a faster
> circuit, and showed some examples. Shai Rotem and Ken Stevens, both
> Intel, discussed timed asynchronous circuits, and the EDA tools
> needed. They needed tools, since it's exploring a new territory."
>
> - An Anon Engineer (from the DAC'99 Trip Report)
From: Steven Nowick <nowick@cs.columbia.edu>
Dear John,
Very amusing comments ("can synthesis about 15 gates"), but quite misguided.
I said our burst-mode CAD tools easily handle MUCH LARGER controllers. In
fact, our tools easily handle functions with dozens of inputs,
implementations with hundreds of gates, etc.
But why build big asynchronous controllers? Very large asynchronous
controllers are naturally built by *decomposing* them into many small and
fast *concurrently communicating components*. This is PARALLEL HARDWARE,
not monolithic central control. It is a different architecture (and
mindset) from the synchronous approach.
Intel and others prefer small light-weight asynchronous controllers,
because you can build faster systems with them. Very large control blocks
can easily be built in this way!
(Anyway, some entertaining comments.)
- Steven Nowick
Columbia University New York, New York
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