( ESNUG 324 Item 13 ) --------------------------------------------- [8/04/99]
Subject: Advantages Of Writing Synthesizable Testbenches For Your Designs
> Hello, Is there any practical use of synthesized testbenches?
> Does it help simulation in any way?
>
> - Shardendu Pandey
From: rajesh52@hotmail.com ( Rajesh Bawankule )
I have seen some companies creating synthesized testbenches to test complex
hardware in short time. They design a chip, preferrably a FPGA, which
generates complex test environment scenario.
Test bench code which is synthesizable is put in tester FPGA. Benefits:
- Test bench runs with your prototype chip at much higher speed.
Generally 1-10 MHz.
- Test bench can be modified by setting different environment parameters.
This generally done with accompanying driver etc.
If your questions is regarding writing testbenches in synthesizable style
purely for simulation then I think it is waste of time. Instead of that
one should write behavioral code. Behavioural code is easy to create,
understand and maintain. It can also generate various test bench
conditions with few lines of code.
- Rajesh Bawankule
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From: tims@synopsys.com (Tim Schneider)
The other thing to think about... if you're planning on targeting an
accellerator/emulator, then a synthesized tbench can be of great benefit.
Usually difficult to implement though.
- Tim Schneider
Synopsys
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From: jcooley@world.std.com (John Cooley)
Yes, cycle-based simulators like Cyclone (or hybrid cycle-compiled
simulators like VCS w/ Roadrunner) run MUCH faster with synthesizable
test benches because everything's reduce-able to equation form with
NO time delays. Everything ticks on the clock edge. Have a test bench
in an event driven simulator and it all depends on the event traffic
you have to determine run time (but, generally, event-driven sims can
run as slow as 1/20th a cycle-based sim -- as a rough rule of thumb.)
- John Cooley
the ESNUG guy
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From: msullivan@ti.com ( Mike Sullivan )
Adding to what John said, beyond simulation it also allows for
porting into the emulation (Quickturn) environment. As well as other
functional verification tools that require synthesizable hardware...
- Mike Sullivan
Texas Instruments
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From: Jacob_Daniel <myhandle@lucent.com>
Could someone please explain to me the difference between a cycle based
simulator and an even driven one, or the relationship between the two
- Jacob Daniels
Lucent Technologies
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From: mench@mench.com ( Paul Menchini )
Loosely speaking, an event-driven simulator simulates those devices whose
inputs have changed. The idea is that devices whose inputs are stable
don't change state or their outputs and therefore may be ignored at the
present simulated time. If the proportion of "active" devices is small,
simulation is faster than simulating every device at every time point.
Similarly, a cycle-based simulator tries to gain speed by simulating
devices only on the edges of clocks. Everything that occurs between clock
edges is modeled using unit delay (or no delay, depending on the tool).
- Paul Menchini
Cadence ( a la OrCAD ) Durham, NC
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