( ESNUG 325 Item 4 ) ---------------------------------------------- [8/18/99]
From: Toby Schaffer <jtschaff@eos.ncsu.edu>
Subject: Ver. 99.7 of the NSCU Cadence Design Kit Is Now Available For Users
John,
We are pleased to announce the availability of version 0.99.7 of the North
Carolina State University Cadence Design Kit (NSCU CDK). This patch has
lots o'stuff; the major additions and changes are:
- overhaul of Diva capacitor extraction to use multiLevelParasitic();
size of extraction rules files is reduced by factor of four
- compliance with SCMOS User's Manual 7.3
- parasitic capacitances for TSMC 0.3um
- wirebond pads and updated transistor models for Supertex (formerly
Orbit) 2.0um
- high-resistance implant layer for AMI C5N
There are other changes, fixes, and updates as well. A complete changelog
is at http://www.ece.ncsu.edu/cadence/CDKpatches.html .
What is the NCSU CDK?
---------------------
The kit focuses on providing a flow for full-custom IC design through MOSIS,
including schematic entry, Verilog digital simulation, analog circuit
simulation, layout DRC checking and device extraction, and mask generation.
It supports 4.4 and is not backward compatible with 4.3.x. All SKILL code
is available as source in a fairly-well organized fashion.
The CDK homepage is http://www.ece.ncsu.edu/cadence/CDK.html .
The tools used are Virtuoso, Composer, Analog Artist, DLE and Diva.
In particular, the kit features:
+ support for all MOSIS SCMOS processes/layers, including process-dependent
layers
+ Diva verification: DRC (all rules from SCMOS User's Manual 7.3),
extraction (MOSFETs, high-voltage MOSFETs, cwell/m1-poly/polycap/inter
-metal/parasitic capacitors, vertical NPN BJTs, diodes, poly/poly2
resistors), and LVS
+ layermaps for MOSIS CIF/GDSII import/export
+ Composer with interface to
* HSPICE/Spectre through Analog Artist, with MOSIS-provided
transistor models in place
* Verilog with technology-independent parts
+ technology-independent libaries for analog (eg, RLC, transistors) and
digital (eg, gates) parts. These parts have SKILL code hooked in to
enforce sizing and grid rules (eg, minimum width/length, half-lambda
grid), automatic transistor model selection depending on technology,
and drain/source area/perimeter estimation.
+ technology libraries (ie, one library for every MOSIS SCMOS process)
with parameterized layout cells setup for both manual use and layout
synthesis via DLE
+ MOSIS wirebond pads (Supertex 2.0um; HP 0.4um, 0.6um; AMI 1.2um)
+ various user-friendly GUI enhancements
* simplified library creation and technology file attachment for
MOSIS technologies
* enhanced label creation (Virtuoso)
* click on any object to print info about it in the CIW
* ability to align layout objects (Virtuoso)
* ability to insert likeness of JPEG images into layout (Virtuoso),
(useful for signing, or putting drawings or photos on, chips)
+ documentation of all customizations in either HTML or OpenBook format
A few things the kit does NOT expressly provide support for:
- it doesn't do P&R
- it doesn't provide a standard cell layout library
- it doesn't do digital timing analysis
- it doesn't do parasitic resistance extraction
At present, the CDK needs to be installed $CDS_DIR/local, so the installer
will probably require sysadmin-type permissions, although this will
hopefully change in the near future.
- Toby Schaffer
North Carolina State University
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