( ESNUG 326 Item 7 ) ---------------------------------------------- [8/25/99]
From: Menno Spijker <menno_spijker@mitel.com>
Subject: Damn! Design Compiler (99.05) Won't Give Me *Signed* Comparitors!
Hi John,
I'm having trouble synthesizing signed arithmatic from Verilog. I thought
converting everything to integers would do the trick since integers are
defined in Verilog as 32-bit signed values. However Design Compiler (99.05)
creates unsigned comparators when I compare two integers. Of course, I can
instantiate a signed DesignWare comparator, but I hate to do that since that
makes the Verilog code tool dependent. The thing is that the Synopsys VCS
simulator handles integers correctly as signed. When I check the HDL
Compiler for Verilog Reference Manual, it says on page 4-6; "All comparisons
assume unsigned quantities", apparently regardless if it compares integers
or regs. How do I force DC to synthesize a *signed* comparator without
instantiating or writing my own comparison functions?
- Menno Spijker
Mitel Semiconductor Kanata, Canada
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