( ESNUG 327 Item 3 ) ----------------------------------------------- [9/2/99]
Subject: ( ESNUG 326 #10 ) But Metastability 'Z' Is A Real Issue For FPGAs!
> Will metastabily propagate through logic gates even when they're disabled?
> That is, assume I have an AND gate, with two inputs A & B. Input A is a
> signal with a posibility of being in metastable state. (Say, it is the
> output of a flip flop which has an asynchronous input). Now if I make
> input B at logic zero, during the possible period of A being at metastable
> state, what will be the output of this AND gate? Or the question is as
> simple as, if one input of an AND gate is a metastable input and other
> input is a logic zero, what will be its output? What if it is an OR gate
> with the other input at logic one?
>
> - Rejeesh
From: Greg Dean <Greg.Dean@nsc.com>
Hi, John,
It depends on how the AND or OR gate is implemented. Standard cell or
discrete logic component gates are implemented straightforwardly, and a 0 on
one input of the AND, or a 1 on one input of the OR will block any path from
the other input to the output.
FPGA gates, however, may be implemented as a lookup table, with the A and B
inputs selecting one of four programmed values that make up the truth table
of the gate. During a transition or metastability on an input, it may be
possible that none of the values are selected, resulting in an indeterminate
output.
- Greg Dean
National Semiconductor South Portland, ME
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