( ESNUG 327 Item 4 ) ----------------------------------------------- [9/2/99]
Subject: Seeking The Design And/Or HDL Code To Internally Multiply A Clock
> Will anybody please share to me a simple logic to multiply a clock ( in
> vhdl or verilog). Say 1 Mhz to 2 Mhz. How to keep the multiplied clock's
> duty cycle to perfect or near perfect 50 %.
>
> - ShtlChen India
From: Mark Lancaster <mark.lancaster@motorola.com>
Create two flip-flops. Clock one using the posedge of your clock and the
other using the negedge. XOR their Q outputs. This creates a 50% duty
cycle multiply by 2.
- Mark Lancaster
Motorola
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From: Mark Lancaster <mark.lancaster@motorola.com>
ACK!! Too early. Haven't had my coffee. Ignore this advice.
- Mark Lancaster
Motorola
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From: Anup Kadkol <anup@flowwise.com>
try this, might work
reg CLK2;
always @(posedge CLK or negedge CLK)
CLK2 <= 1'b1;
if (CLK2 == 1)
CLK2 <= #delay 1'b0;
The delay can be varied depending on duty cycle will be 500ns in case of
1 MhZ and 50% duty cycle.
- Anup Kadkol
Flowwise
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From: Rainer Theuer <Rainer.Theuer@sican.de>
Why do you use 1MHz for the master clock ? Implement your design with a
2 MHz master clock and you don't get such problem! :-)
- Rainer Theuer
SICAN GmbH Hannover, Germany
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