( ESNUG 327 Item 9 ) ----------------------------------------------- [9/2/99]
Subject: Insuring You Get Just One DesignWare Full Adder W/ Design Compiler
> I have all the inputs to a full adder. How to write verilog code so that
> after synthesis synopsys uses its own designware fulladder. Now I am doing
> as follows:
>
> assign {cout, sum} = A + B + cin;
>
> But after synthesis it uses two adders from designware library. I want
> cin to go to a "real" Cin.
>
> - Azhar Quddus
> Tampere University of Technology Finland
From: mguthaus@eecs.umich.edu (Matt Guthaus)
In your .synopsys_dc.setup file add this line: hdlin_use_cin = true
- Matt Guthaus
University of Michigan
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