( ESNUG 329 Item 4 ) --------------------------------------------- [9/22/99]
Subject: ( ESNUG 325 #5 ) Beware Of Verilog Uselib! Linking Takes HOURS!
> The first problem I had was that Verilog-XL would try to build the
> support ASIC out of vendor A's library components instead of vendor B's
> library. I was able to solve this problem using the `uselib directive ...
>
> - Greg Arena
> Dialogic Corporation Parsippany, NJ
From: "Paul.Zimmer" <paul.zimmer@cerent.com>
Beware of uselib. We were using it for a while, then discovered that
it made the linking take HOURS during gate simulations (as opposed to
minutes for good-ol' -y). My guess is that uselib was causing us to
troll through the whole search path every time XL had to link a module.
- Paul Zimmer
Cerent Corp.
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