( ESNUG 329 Item 7 ) --------------------------------------------- [9/22/99]
Subject: ( ESNUG 326 #7 ) Tricking DC 99.05 To Get *Signed* Comparitors
> I'm having trouble synthesizing signed arithmatic from Verilog. I thought
> converting everything to integers would do the trick since integers are
> defined in Verilog as 32-bit signed values. However Design Compiler 99.05
> creates unsigned comparators when I compare two integers. Of course, I
> can instantiate a signed DesignWare comparator, but I hate to do that
> since that makes the Verilog code tool dependent. The thing is that the
> Synopsys VCS simulator handles integers correctly as signed. When I check
> the HDL Compiler for Verilog Reference Manual, it says on page 4-6; "All
> comparisons assume unsigned quantities", apparently regardless if it
> compares integers or regs. How do I force DC to synthesize a *signed*
> comparator without instantiating or writing my own comparison functions?
>
> - Menno Spijker
> Mitel Semiconductor Kanata, Canada
From: Menno Spijker <menno_spijker@mitel.com>
Hi John,
An old collegue in the Netherlands, Rob van der Valk, gave me a hint on
how to do the signed comparisons after he saw my letter in ESNUG. The
trick is to invert the MSB's of the operands and do an unsigned
comparison on that.
So instead of:
op_a[n:0] > op_b[n:0]
do:
{~op_a[n],op_a[n-1:0]} > {~op_b[n],op_b[n-1:0]}
That's easier and smaller in logic than the functions I wrote.
- Menno Spijker
Mitel Semiconductor Kanata, Canada
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