( ESNUG 329 Item 16 ) -------------------------------------------- [9/22/99]
Subject: Seven DC Approaches To Eliminating Timing Violations In Designs
> Synopsy dc is not able to meet the timing constraints on a design. After
> analysis, we found that synopsys selects the slowest architecture for the
> design ware (multiplier and adder) rather than the fastest. The design is
> really simple. About 40,000 gates, a single clock feeding all registers.
>
> No problems: check_timing and check_design commands report nothing.
>
> Synopsys version is 99.05. I know that we can select manually the
> architecture for the design ware (set_implementation) but it is tedious.
> Do you have an idea to solve that problem.
>
> - Jean-Marc Allard
From: Predrag Markovic <dmpeca@eunet.yu>
Hello Allard,
Well, you have a lot of options. Their values depend strongly of the type of
design. Generally, I would try the following (not in the given order).
1) Try to exclude (set_dont_use) slow cells from ASIC foundry library.
The foundry usually compile a zillions of cells for DC that you not
need. This number of cells creates enormous design (mapping) spaces
for DC that can not be solved (NP bounded). Look at your timing
report and find the cells with unreasonable high delay for the given
technology. set_dont_use and repeat compilation.
2) Try incremental compiling i.e. compiling in "two rows", second
with this switch.
3) At some level of hierarchy apply boundary_optimization. That could
be extremely effective, particularly if you have applied bottom up
approach compiling your design. If you have some "unreasonable"
buffers in you design introducing delay that will be very effective.
Where in within the chip hierarchy to apply boundary_optimization
is difficult to say. Sooner is better than latter.
4) Try to identify the critical path and apply 2) and 3).
5) Analyze the fan out of the nets. set_max_fanout to smaller number
can help also.
6) If you have used operator inferencing (and BOA) in you HDL code rather
than DW component instantiation than change HDL code to use DesignWare
component instantiation. This can give better DC results in some cases
and give you much better control during the synthesis.
7) Keep the number of gates in current_design for compile command to up
to a few thousand.
Other options could be tedious as you said. Hmm... maybe set_implementation
is not so tedious as it looks like.
- Predrag Markovic
DMPECA Belgrade, Serbia
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