( ESNUG 330 Item 7 ) --------------------------------------------- [9/30/99]
Subject: ( ESNUG 328 #6 ) Those Complicated DC Wireload Issues Continue
> I did a real quick test setting the top level of a design to a certain
> wireload, with all the subdesigns having no wireload. The results were
> the same as setting all designs to that same wireload. The timing for
> having no wireload whatsoever set was different, so this supports that
> designs with no wireload do indeed inherit them from parent hierarchy.
>
> - [ A Synopsys CAE ]
From: Robert Wiegand <rwiegand@ensoniq.com>
Hi John,
I found another interesting wireload "behavior" that I didn't expect
involving enclosed mode and switching between operating conditions. Let's
start with a hierarchical design compiled bottom up, with the wireload
specified for each design based on design size, using enclosed mode. Each
design is compiled, dont_touch'ed, and saved without the -hierarchy switch
(compile generated hierarchy such as designware and mux-ops are ungrouped
after the compile) ensuring that higher level designs will link in the
previously compiled lower level designs without trying to recompile them.
As expected, the wireloads set on the lower level designs will "stick" (as
if they were design attributes) when they are linked in by higher level
designs. A core level timing report will show all the subdesigns and their
respective wireloads as expected.
The unexpected behavior occurs after changing operation conditions. I do
the lower level compiles at max conditions, but at the core level I do a
min/max fixup step, and check the results at min, typ, max and minmax
conditions. Changing conditions on the fly (without reloading the design)
includes the following steps:
1) unload old libraries and reload new libraries if they are different
2) update the link_library and target_library variables
3) perform any library initialization steps such as dont_use'ing specific
cells, etc
4) set the wireload on the current design
5) set the operating conditions on the current design
6) redefine the clocks on the current design (insertion delays are
different)
The core level timing report no longer shows the subdesign wireloads! The
above listing of steps is abreviated, and I haven't isolated exactly which
command makes the subdesign wireload behavior change. The timing results
are consistant with using an enclosed wireload at the core and not setting
the subdesign wireloads i.e., the core wireload is used for the entire
design. Changing to one of the subdesigns and doing a report_design gives
different results depending on whether or not there is a default wireload
attribute on the library. With a library default wireload, the report
shows the wireload as manually selected by user, but the wireload is the
default wireload, not the desired one. Without a library default wireload,
the report shows no wireload specified.
In either case, it is still the core wireload that is used throughout the
design. I tried this on several libraries, including one where all
condtions are in the same library, and another with seperate min, typ and
max libraries. The results were the same.
In order to get around this, and return to the desired and expected
behavior, I modified my scripts for changing operating conditions to set
the wireload on each and every design in the hierarchy. Something like
this:
which project_name + "_wireload.scr"
if (dc_shell_status) {
echo "Using hierarchical wireloads"
foreach (des, find(design)) {
current_design des
include project_name + "_wireload.scr"
} else {
echo "Using default wireload"
current_wireload = wireload_load
foreach (des, find(design)) {
current_design des
set_wire_load -library wireload_library -mode wireload_mode
current_wireload
}
}
current_design core
The script referred to by project_name + "_wireload.scr" is a brute force
search and destroy script to match up the current_design design name with
an associated wireload. This worked great until I tried to route the scan
chains at the core level, which changes the design names! The variable
insert_test_design_naming_style can be used to control how the design is
renamed, but the %s and %d fields are required. I set it to %s_scan_%d.
Since I couldn't find any quick and easy way to prevent the renaming from
occuring, I had to resort to more brute force. The wireload script looks
something like this:
/* get design_name as a string */
root_design {}
design_name = ""
foreach (root_design, find(design, current_design)) {}
design_name = root_design
/* assign wireload to design_name */
if (design_name = = top_block){
current_wireload = [top wireload]
} else if (design_name == core_block \
|| design_name == core_block + "_scan_1")
{ current_wireload = [core wireload] }
else if (design_name == "block1" || design_name == "block1_scan")
{ current_wireload = [block1 wireload]}
else if (design_name == "blockn" || design_name == "blockn_scan")
{ current_wireload = [blockn wireload] }
else {
echo "Design not found in wireload script, using default wireload"
current_wireload = wireload_load
}
set_wire_load -library wireload_library -mode wireload_mode
current_wireload
My timing reports now show all the correct and expected subdesign
wireloads, and the timing results are consistant with the expected wireload
behavior.
- Bob Wiegand
Creative Labs Malvern, PA
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